TQ2440 Development Board Learning Documentary (3)---Set the clock frequency to make the CPU run faster

0 principle 0.1 where the clock originates

The so-called clock, is the voltage level change, only the constant 0,1 alternating change, the CPU can be driven to run. The s3c2440 supports a variety of clock sources, which are selected by the CPU pins OM3 and OM3. For the QT2440 board, OM3 and OM2 are directly grounded, which means that the clock source from the pin XTIPLL and XTOPLL, the two pins on the core board of TQ2440 is connected to a 12MHz crystal oscillator.

Clock principle and setting of 0.2 s3c2440

Different devices, such as CPUs, RAM, and UART, require different clock frequencies to operate, and these different frequencies need to be provided through a frequency conversion circuit called the PLL (Phase Locked Loop) in the electronics industry. As a software-born programmer, it is unlikely to be proficient in circuit design, just know that the PLL can convert the input clock to many other different clocks for the system to use.

Fin (12MHZ)---(PLL variable frequency)--–>fclk, HCLK, PCLK

The relationship between the output frequency and the input frequency is controlled by the register of the response. The settings for the control parameters are described in detail in the s3c2440 data sheet. Here are just a few of the areas that are especially important.

2. If Hdivn is not 0, the CPU bus mode have to was changed from the fast bus mode to the asynchronous
   Bus mode using following instructions (s3c2440 does not support synchronous bus mode).
   Mmu_setasyncbusmode
   MRC p15,0,r0,c1,c0,0
   Orr R0,r0, #R1_nF: Or:r1_ia
   MCR p15,0,r0,c1,c0,0
   If Hdivn is not 0 and the CPU bus mode is the Fast bus mode, the CPU would operate by the HCLK.
   This feature can is used to change the CPU frequency as a half or more without affecting the HCLK
   and PCLK.
   In other words, s3c2440 does not support asynchronous bus mode (s3c2440a support). So only working in fast bus mode, if HDIVN is not 0, the driver CPU will not be FCLK, but hclk.

4. Fclkout must is bigger than 200MHz (It does not mean that the ARM core have to run more than 200MHz). Because the CPU may work with HCLK, as shown in the first article.

6. When you set MPLL&UPLL values, you had to set the UPLL value first and then the MPLL value. (Needs intervals
   Approximately 7 NOP. That is, UPLL is set to be spaced at least 7 NOP before the MPLL is set.

8. If MPLL is not set, then the CPU will always run at the fin frequency clock.
10. The formulas for MPLL and UPLL are not exactly the same.

MPLL Control RegisterMpll = (2 * m * Fin) / (p * 2S)m = (MDIV + 8), p = (PDIV + 2), s = SDIVUPLL Control RegisterUpll = (m * Fin) / (p * 2S)m = (MDIV + 8), p = (PDIV + 2), s = SDIV

1 Key Code Description

Although the theory is slightly more complex, the actual setup code is very simple. The end result we want to set is: Fclk=200mhz, and the CPU runs on it. Of course, according to the data in the manual, set to a higher frequency, but after the attempt to find the high frequency CPU heat is obvious, in order to protect the test board, the use of a lower fclk.

/ * Fin=12mhz, Fclk=200mhz * /. EquMpllcon,0x4c000004. EquM_mdiv, the. EquM_pdiv,4. EquM_sdiv,1/ * Fin=12mhz, UPLLCLK = 48MHz * /. EquUpllcon,0x4c000008. EquU_mdiv, About. EquU_pdiv,2. EquU_sdiv,2/ * HCLK=FCLK, PCLK=FCLK, UCLK=UPLLCLK * /. EquCLKDIVN,0x4c000014/ * If HDIVN is not 0 and the CPU bus mode is the Fast bus mode, the CPU would operate by the hclk*/. EquHDIVN,0. EquDIVN_UPLL,0. EquPDIVN,0LdrR0, =clkdivn LDRR1, = (divn_upll<<3) + (hdivn<<1) + pdivn StrR1, [R0] LdrR0, =upllcon LDRR1, = (u_mdiv<< A) + (u_pdiv<<4) + U_sdiv StrR1, [R0]NOP    NOP    NOP    NOP    NOP    NOP    NOPLdrR0, =mpllcon LDRR1, = (m_mdiv<< A) + (m_pdiv<<4) + M_sdiv StrR1, [R0]

2 Test Instructions

We still use the same as the previous post of the same LED water lamp C program, but because the CPU operating frequency increased from 12MHz to 200MHz, the speed of running lights than the previous version of the change is very obvious, it is also intuitive to verify that we set the CPU clock success.

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TQ2440 Development Board Learning Documentary (3)---Set the clock frequency to make the CPU run faster