[Translation]. Calculate the depth of FIFO

ArticleDirectory

• Introduction
• Example: FIFO deep computing

Original article: http://www.asic-world.com/tidbits/fifo_depth.html

Introduction

One of the most frequently asked questions during interviews is how to calculate the depth of FIFO. Knowledge tells us that when the read rate is slower than the write rate, the FIFO can be used as a buffer element or queue in the system. Therefore, the size of FIFO basically implies the capacity of the data to be cached, which depends on the read/write speed. According to statistics, the data rate of the system depends on the load capacity of the system. Therefore, to ensure the size of the FIFO, we need to consider the worst case of FIFO transmission.

In the worst case, what is different from maximizing the read/write rate. For read operations, the maximum data rate should be considered; for write operations, the minimum data rate should be considered.

In this case, the data rate of read operations is determined by the data in the idle period. The maximum data rate of write operations should not be considered as the idle period.

In write operations, we need to know the data rate, that is, the number of data * clock rate. The write side is the source side, while the read side is the destination side. The data rate of the read operation depends on the data rate on the side of the write and its own read rate, that is, FRD/idle_cycle_rd.

To understand the data rate of write operations, we need to know the number of data in the burst transmission. We set it to B.

Keep up with the previous issue, then the FIFO size = cache size = B-B * FRD/(fwr * idle_cycle_rd ).

The synchronization latency of asynchronous read/write is not discussed here. The larger the synchronization latency, the larger the FIFO size is required to cache more write data.

Example: FIFO deep computing

Suppose we need to design a FIFO that meets the following requirements, and we want to calculate the minimum FIFO depth.

1. Asynchronous FIFO
2. Write clock 30 MHz F1
3. Read clock 40 MHz F2
4. Burst write data size B
5. Case 1: The read end has an idle clock period I
6. Case 2: The read end has 10 idle clock period I

FIFO deep computing = B-B * F2/(F1 * I)

If we change the read cycle, that is, there is one idle cycle between two read cycles, then the FIFO depth = B-B * F2/(F1 * 2)

In our current problem, FIFO depth = B-B * 40/(30*2) = B (1-2/3) = B/3

This means that if the data capacity for burst transmission is 10, the FIFO depth is = 10/3 = 3.3 = 4 (approximate)

If B = 30, the FIFO depth = 20/3 = 6.6 = 7

If there are 10 idle cycles in two read cycles, the FIFO depth = B-B * F2/(F1 * 10) = B (1-4/30) = B * 26/30