Translation: Intel CPU Architecture History

The source of this article is major componets of computer "engine" written by Professor noraml matloff. This article is a bit old and has some meanings :-)

History of Intel CPU Structure

The earliest widely-used Intel processor chip was the 8080. Its word size was 8 bits, and it has ded registers
Named A, B, C and D (and a couple of others). Address size was 16 bits.
The next series of Intel chips, the 8086/8088, and then the 80286, featured 16-bit words and 20-bit addresses.
The, B, C and D registers were accordingly extended to 16-bit size and renamed ax, BX, CX
And dx ('x' stood for "extended"). Other miscellaneous registers were added. The lower byte of ax was
Called Al, the higher byte ah, and similarly for Bl, BH, etc.

The earliest widely used Intel processor is 8080. It has 8 characters, including a, B, c, d (and some others) registers, and the address length is 16 bits. The next intel chip is 8086/8080, followed by 80286, with a 16-bit length and a 20-bit address length. Registers A, B, C, and D are also extended to 16 bits and named ax, BX, CX, dx ('x' stands for "extended "). Registers for various functions are also added. Ax's low position is called Al. The high position is also called Ah, BL, and BH.

Beginning with the 80386 and extending to the Pentium series, both word and address size has been 32 bits.
The registers were again extended in size, to 32 bits, and renamed eax, EBX and so on ('E' for "extended ").
The pre-32-bit intel CPUs, starting with 8086/8088, replaced the single register PC with a pair of registers,
CS (for code segment) and IP (for instruction pointer). A rough description is that the CS register pointed
The code segment, which is the place in memory where the program's instructions start, and the IP register
Then specified the distance in bytes from that starting point to the current instruction. Thus by combining
The information given in C (CS) and C (IP), we obtained the absolute address of the current instruction.

From 80386 to the Pentium series, the length of the word length and the address length are changed to 32 bits, and the registers are also extended to 32 bits, known as eax, EBX ('E' stands for "extended "). For 32-bit intel CPUs, replace a single PC register with a pair of registers, CS (code segment) and IP (Instruction Pointer) from 8086/8088 ). A rough description is that the CS register points to the code segment, that is, the place where program commands start to be executed in the memory. The IP register then specifies the distance from the current instruction to the starting point expressed in bytes. In this way, we can get the absolute address of the current command through the combination of the two.

This is still true today when an Intel CPU runs in 16-Bit mode, in which case it generates 20-bit addresses.
The CS register is only 16 bits, but it represents a 20-bit address whose least significant four bits are implicitly
0 s. (This implies that code segments are allowed to begin only at addresses which are multiples of 16 .)
The CPU generates the address of the current instruction by concatenating C (CS) with four 0 bits and then
Adding the result to C (IP ).

This still seems correct today. If the Intel CPU runs in 16-Bit mode, in this case, it generates a 20-bit address. The CS register only has sixteen bits, but it does represent a 20-bit address. This implies that the minimum 4 bits of the address are '0 '. (This indicates that the code segment can only start at an address multiple of 16 ). The CPU obtains the current instruction address by adding four '0' bits to CS and the IP value.

Suppose for example the current instruction is located at 0x21082, and the code segment begins at 0x21040.
Then C (CS) and C (IP) will be 0x2104 and 0x0042, respectively, and when the instruction is to be executed,
Its address will be generated by combining these two values as shown above.

Assuming that the current command status is 0x21082 and the code segment starts from 0x21040, the Cs and IP addresses should be 0x2104 and 0x0042 respectively. When the command is executed, its address is the sum of the two values above.

The situation is similar for stacks and data. For example, instead of having a single SP register as in our
Model of a typical CPU above, the earlier intel CPUs (and current CPUs when they are running in 16-bit
Mode) use a pair of registers, SS and sp. SS specifies the start of the stack segment, and SP contains
Distance from there to the current top-of-stack. For data, the DS register points to the start of the data
Segment, and a 16-bit value contained in the instruction specifies the distance from there to the desired data
Item.

Stack and data are similar. For example, early intel CPUs (and current CPUs running in 16-Bit mode) used a pair of registers, SS and SP, instead of using a single SP register as a typical CPU. The SS specifies the start of the stack segment. The SP contains the distance from where to the top of the stack. For data, the DS register points to the beginning of the data segment, and a 16-bit value in the instruction specifies the distance to the required data item.

Since IP, SP and the data-item distance specified within an instruction are all 16-bit quantities, it follows
That the code, stack and data segments are limited to 216 = 65,536 bytes in size. This can make things quite
Inconvenient for the programmer. If, for instance, we have an array of length, say, 100,000 bytes, We cocould
Not fit the array into one data segment. We wocould need two such segments, and the programmer wowould have
To include in the program lines of code which change the value of C (DS) Whenever it needs to access a part
Of the array in the other data segment.

Because the distance between IP, SP, and the data specified in the command is 16 bits, the length of the code segment, stack segment, and data segment is limited to 216 = 65,536 bits. This is inconvenient for programmers. For example, if the length of an array is 100,000 bytes, we cannot put it into a data segment. We need two such segments, and when the programmer needs to access the array in the other segment, the code that changes the DS value needs to be placed in the code line.

These problems are avoided by the newer operating systems which run on Intel machines today, such
Windows and Linux, since they run in 32-Bit mode. addresses are also of size 32 bits in that mode, and IP,
SP and data-item distance are 32 bits as well. Thus a code segment, for instance, can fill all of memory, and
Segment switching as your strated above is unnecessary.

Today, these problems are avoided by new operating systems running on Intel machines, such as Windows and Linux, because they are running in 32-Bit mode. In this mode, the IP address is also 32-bit, and the distance between the IP address and the SP address is the same. Such a code segment can fill up the entire memory, and segment switching like above is no longer needed.

I found that this paragraph does not mean too much, but I still insisted on turning it over.
It took more than an hour to get started.