Transplantation of real-time operating system μC/OS-II on MCF5272

 

Keywords:μC/OS-II MCF5272 port GNU tool chain

 

As a Real-Time Kernel, μC/OS has become familiar to people since 1992, and has now evolved into μC/OS-II. Javasc/OS-II supports a maximum of 56 tasks, whose kernel is preemptible, always executes the highest priority tasks in the ready state, and supports semaphore (semaphore), mailbox (Mailbox) message Queue and other common inter-process communication mechanisms. Unlike most commercial RTOS, the μC/OS-II exposes all source code and can be obtained free of charge, charging a small amount of license fees for commercial applications. Generally, commercial operating systems such as VxWorks, PSOs, and wince are charged for tens of thousands of US dollars. In addition, each product has to pay the operation fee, resulting in high development and use costs.

Currently, MCF5272 is a ColdFire processor with the highest integration level. It adopts the ColdFire V2 variable-length CPU core and digitaldna technology to achieve 63dhrystone2. 1 MIPS at a 66mhz clock. Its internal SIM (System Integrated Module) Unit integrates a wide range of general modules, such as 10/100 MHz Fast Ethernet controller, USB interface, etc, moreover, it can be seamlessly connected to common peripheral devices (such as SDRAM and ISDN transceiver), which simplifies the design of peripheral circuits and reduces product costs, volumes, and power consumption.

Use the GNU toolchain (including the cross compiler GCC, assembler as, etc.) to compile the μC/OS-II kernel, the host (host) environment is 16 mb sdram. Compile the executable code of the MCF5272 processor on the host machine and download it to the target board for debugging and running through the MCF5272 BDM debugging tool.

1 μC/OS-II System Structure

Figure 1 illustrates the software and hardware architecture of μC/OS-II. The application is on the top of the entire system, and each task can think that it excludes the CPU, so it can be designed as an infinite loop. Code unrelated to the μC/OS-II processor provides systems services for the μC/OS-II that applications can use for memory management, inter-task communication, and creation and deletion of tasks.

Most of the μC/OS-II code is written in ansi c language, so the portability of μC/OS-II is better. However, you still need to use C and assembly languages to write some processor-related code. The transplantation of μC/OS-II must meet the following requirements:

(1) The C compiler of the processor can generate reusable code;

(2) You can use the C call to access and exit the critical code (critical Code );

(3) The processor must support hardware interruptions and require a scheduled interrupt source;

(4) The processor needs a hardware stack that can hold certain data;

(5) The processor must have instructions that can exchange data with memory and stack in the CPU register.

The main work of the OS-II is to write the relevant code of the processor and compiler and BSP.

2 μc/OS-II DSP Coding

BSP (board-level support package) is a software layer between the underlying hardware and the operating system. It initializes the initial hardware and software after the system is powered on and encapsulates the underlying hardware, so that the operating system no longer faces specific operations.

Compile a simple BSP for the μC/OS-II. It first sets the internal registers of the CPU and the system stack, initializes the stack pointer, and establishes the running and calling environment of the program. Then, it can conveniently set the MCF5272 address (CS0 ~ Cs7), gpio, and SDRAM Controller, initialize the serial port (uart0) as the default print port, and provide some hardware-Related Routines and functions such as dprintf () to the operating system for debugging; after the CPU, board level, and program initialization are complete, you can control the CPU to the operating system.

The MCF5272 processor uses system power-on as the No. 2 exception. Therefore, you must enter the physical address of the first command in the corresponding position in the exception vector table, which can be automatically completed during compilation. The vector table must be stored in the Flash corresponding to CS0 for automatic reading when the CPU is powered on. For example:

_ Vectors: // start address of the vector table

. Long 0x0, _ start, _ fault, _ fault ,... // Initialize the 1k byte vector table

......

_ Start: NOP // The First Command

Move. W #0x2700, % Sr // shield all interrupts

Move.1 # _ vectors, % D0

Move. C % D0, % VBR // # vectors-> VBR

Move.1 #0x10000001, % D0

Move. C % D0, % mbar // base address of the sim unit 0x10000000

Move.1 #0x20000001, % A0 // The starting address of SRAM 0x20000000

Move. C % A0, % rambar0 // initialize internal SRAM

Move.1 #0x20001001, % A7 // set the stack pointer

......

JSR cpu_init // call cpu_init to initialize the sim Unit

JSR ucos_start // start μC/OS-II

......

The cpu_init function is used to initialize the sim unit inside the CPU, the SDRAM controller, and The UART serial port. It is worth noting that the initialization sequence of SDRAM varies from manufacturer to manufacturer.

After completing disk-level and board-level initialization, BSP is also responsible for initializing the program itself, such as copying the content of the. Data segment from the read-only Rom to the SDRAM to create a runtime environment. The following code creates a program data segment:

Memcpy (& _ sdata, & _ etext, (& _ edata-& _ sdata); // copy the. Data Segment

Memset (& _ sbss, 0, (& _ ebss-& _ sbss); // clear the. BSS segment

You also need to write 4 simple assembler functions for the μC/OS-II. After each hardware clock arrives, the μC/OS-II will call osintctxsw () in the interrupt service routine for job scheduling; and when a job is suspended for waiting for resources, you do not have to wait until all your time slices are used up. You can take the initiative to discard the CPU, which can be achieved by calling a task-level task scheduling function osctxsw. Osintctxsw () is relatively complex (). Because ostickisr () calls osintexit (), osintexit () calls osintctxsw () again. If you perform task switching, neither call will return, different C compilers and different compilation options use different stacks to process C calls. Therefore, osintctxsw () is related to the compiler. GCC is in use 2 ~ During Level 4 optimization, a jsr jump command is used in the main function, and the number of transferred messages starts with linkw % FP, # <D0>. Both commands affect the stack pointer. To Implement Task Switching, you must re-adjust the stack pointer to compensate for the impact of the call. A complete process is as follows:

Osintctxsw:

Adda.1 #16, % A7 // stack compensation, GCC-O2->-04 optimized

Move.1 (ostcbcur), % A1

Move.1 % A7, (% A1) // ostcbcur-> ostcbstkptr = Sp

JSR ostaskswhook // reconcile the hook function

/* Ostcbcur-> ostcbstkptr = ostcbhighrdy-> ostcbstkptr */

Move.1 (ostcbhighrdy), % A1

Move.1 % A1, (ostcbcur)

Move. B (ospriohighrdy), % D0

Move. B % D0, (ospriocur) // ospriocur = ospriohighrdy

Move.1 (% A1), % A7 // sp = ostcbcur-> ostcbstkptr

Movem.1 (% A7), % D0-% D7/% A0-% A6 // resume the CPU register, switch to the new task

Lea 60 (% A7), % A7

RTE

The space limit is not described in the other three functions.

3 μC/OS-II Task Stack Initialization

Each task in the μC/OS-II has its own job stack, Which is initialized by ostaskstkinit () at the beginning of job creation. The purpose of stack Initialization is to simulate an interruption. The task stack stores the starting address of the task code and some CPU registers (initial values are irrelevant). Once the conditions are met, the task can be executed. When an interruption occurs, MCF5272 automatically saves the program pointer PC, Status Register SR, and other information, which is in a four-character frame structure. In addition, % D0-% D7 and % A0-% A6 must also be added to the stack in a certain order. After completing the stack initialization, ostaskstkinit () also returns the stack top pointer for the initialization of the TCB structure of the task control block. This program is written in C language.

4 μC/OS-II system clock

The MCF5272 processor has four built-in timers and uses timer0 to generate a scheduled interrupt of 10 ms in a cycle as the system clock. When the pivr register is set to 0x40, timer0 is interrupted at 69. Enter the entry address of the clock service program ostickisr () at the corresponding position of the vector table and initialize the clock:

Volatile unsigned short * ptimer;

Ptimer = (unsigned short *) (0x10000000 + 0x200); // point to timer0

/* Reset the clock */

* Ptimer & = 0xfff9; // The timer is in the Stop State.

* Ptimer = (* ptimer & 0x00ff) | 0xfa00; // pre-division = 250

* Ptimer | = 0x0018; // when the count is full, it is automatically cleared and interrupted

Ptimer [2] = 165; // set TRR = 165

* Ptimer = (* ptimer & 0xfff9) | 0x0004; // CLK = Master/16, start

The clock cycle of the above section is: (1/66 MHz) × 250 × 164 × 16 = 0.01 seconds. More precise Clocks can be used in scenarios with high real-time requirements. Once timer0 Initialization is complete, it starts to work. However, to enable interruption, you must also set the relevant fields in the Register to assign IPL (Interrupt priority level, interrupt priority) to the interrupt ), the interrupt is not blocked by the initial status register Sr.

The clock initialization code can be placed in the first μ c/OS-II task and executed after osstart. Once the kernel can perform normal task switching, the porting is basically completed.

5. kernel compilation and download

All C and Assembly source files are compiled and linked to form a binary image file. Since the μC/OS-II uses a custom data type, it must be converted to a type that GCC (gnu c compiler) can recognize, for example, int8u can be defined as unsigned char. In addition, you must write a LD (link script) file to control compilation and locate the program to the actual ROM and ram resources. For convenience of debugging, the BDM tool is usually used to download the kernel to the target board SDRAM for running. After the debugging is passed, the kernel is solidified into flash.

RTOS is a feature of embedded applications. The Application of RTOS can make the product more reliable, more powerful, and shorter development cycle. μC/OS-II has good real-time and small amount of code, and has been widely transplanted to x86, 68 K, ColdFire, nm8xx, arm, MIPS, c5409 and many other processors. Hundreds of successful commercial application examples demonstrate that μC/OS-II is a stable and reliable kernel, so porting μC/OS-II to MCF5272 has a strong practical prospect.

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