TTL level, CMOS level, 232/485 level, OC Gate, OD gate Basics

1.rs232 level

Or the serial level, some even say the computer level, all these statements, refers to the computer 9-pin serial port (RS232) level, using negative logic,

-15v ~ -3V Rep 1

+3V ~ +15v Rep 0

2.rs485 and RS422 level

Since both use differential transmission (balanced transmission), so they are level mode, generally have two pin, a, b

Voltage difference between the sending side AB

+2 ~ +6v:1

-2 ~ -6v:0

Voltage difference between the receive-side AB

Greater than +200mv 1

Less than -200mv 0

Defines the state of logic 1 as b>a;

Defines the state of logic 0 as a>b.

The voltage difference between AB is not less than 200mv.

3.USB

The power cord is 5V, providing the USB device with a maximum of 500mA of current, independent of the level on the data line, the data line is a differential signal, usually d+ and D-varies between +400mv~-400mv.

In traditional single-ended (single-ended) communication, a line transmits a bit. The high level is 1 and the low level is 0. In the event of interference in the data transmission process, the high and low level signal is likely to result in a large disturbance of the critical value, and the signal will go wrong once the higher level or low level signal exceeds the critical value. In the differential transmission circuit, the output level is positive voltage is expressed in logic 1, the output negative voltage is the logic 0, and the output 0 voltage is meaningless, it does not represent 1, does not mean 0. In the differential communication, the interfering signal enters the adjacent two signal lines simultaneously, and at the signal receiving end, two identical interfering signals enter the two inverting inputs of the differential amplifier respectively, and the output voltage is 0. Therefore, the differential signal technology has strong immunity to the jamming signal. For serial transmission, LVDS can withstand external interference, while for parallel transmission, LVDS can not only resist external interference, but also can resist crosstalk between data transmission lines. As a result of the above reasons, as long as the actual circuit using low-voltage differential signal (Voltage differential Signal, LVDS), the amplitude of about 350mV can meet the requirements of near-distance transmission. Assuming that the load resistance is 100 kohm, when using LVDS transmission data, if the twisted pair length is 10m, the transmission rate can reach 400Mbps, when the cable length increases to 20m, the rate will be 100Mbps, and when the cable length is 100m, the rate can only reach 10Mbps around

4. Transfer rate

One-to-one connector case

RS232 can achieve two-way transmission, full-duplex communication maximum transmission rate of 20kbps;

RS422 can only do one-way transmission, half-duplex communication, the highest transmission rate of 10Mbps;

RS485 bidirectional transmission, half-duplex communication, maximum transmission rate 10Mbps;

USB can automatically select one of the three modes of HS (high-speed, high-speed, 480Mbps), FS (Full-speed, full speed, 12Mbps) and LS (low-speed, low speed, 1.5Mbps).

The rs-422/485 and RS-232 are the interface standard of the serial port, the rs-422/485 is the differential input output, RS-232 is the single-ended input and output.

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Common logic levels

Logic level: TTL, CMOS, LVTTL, ECL, PECL, gtl;rs232, RS422, LVDS, etc.
The logic level of TTL and CMOS can be divided into four categories according to typical voltage: 5V series (5V TTL and 5V CMOS), 3.3V series, 2.5V series and 1.8V series.
The 5V TTL and 5V CMOS logic levels are common logic levels.
Logic levels of 3.3V and below are referred to as low voltage logic levels and are commonly used as lvttl levels.
The logic level of low voltage also has 2.5V and 1.8V two kinds.

TTL: Transistor-transistor logic transistors.

vcc:5v;

voh>=2.4v;vol<=0.5v;

vih>=2v;vil<=0.8v.

Because there is a lot of idle between 2.4V and 5V, there is little benefit in improving the noise tolerance, and it will increase the power consumption of the system and also affect the speed. So I cut off a part of it later. That's the back of the Lvttl.

The Lvttl is also divided into 3.3V, 2.5V, and lower voltage lvttl (Low Voltage TTL).

3.3V LVTTL:

vcc:3.3v;

voh>=2.4v;vol<=0.4v;

vih>=2v;vil<=0.8v.

2.5V LVTTL:

vcc:2.5v;

voh>=2.0v;vol<=0.2v;

vih>=1.7v;vil<=0.7v.

The lower Lvttl is not used first. Multi-use in the processor and other high-speed chips, when used to view the chip manual is OK.

TTL usage Note: TTL level is generally more severe overshoot, may be at the beginning of the string 22 Kohm or 33 ohms, TTL level input pin is internally considered high level. To drop the words apply 1k below the resistor drop down. The TTL output does not drive the CMOS input (plus pull).

CMOS: Complementary l Oxide Semiconductor Pmos+nmos.

vcc:5v;

voh>=4.45v;vol<=0.5v;

vih>=3.5v;vil<=1.5v.

The relative TTL has a greater noise tolerance, and the input impedance is much larger than the TTL input impedance. corresponding to the 3.3V LVTTL, there is a lvcmos, which can be directly driven with the LVTTL of 3.3V.

3.3V LVCMOS:

vcc:3.3v;

voh>=3.2v;vol<=0.1v;

vih>=2.0v;vil<=0.7v.

2.5V LVCMOS:

vcc:2.5v;

voh>=2v;vol<=0.1v;

vih>=1.7v;vil<=0.7v.

CMOS use note: The CMOS structure has a controllable silicon structure inside, when the input or input pins higher than a certain value of VCC (such as some chips are 0.7V), the current is large enough, it may cause latch effect, resulting in the chip burning.

ECL: Emitter coupled logic emitter-coupled logical circuit (differential structure)

vcc=0v;vee:-5.2v;

VOH=-0.88V;VOL=-1.72V;

vih=-1.24v;vil=-1.36v.

The speed is fast, the driving ability is strong, the noise is small, it is easy to reach hundreds of m application. However, the power consumption is large and negative power is required. To simplify the power supply, there was a pecl (ECL structure, switched to positive voltage) and lvpecl.

Pecl:pseudo/positive ECL

vcc=5v;

voh=4.12v;vol=3.28v;

vih=3.78v;vil=3.64v

Lvpelc:low Voltage PECL

vcc=3.3v;

voh=2.42v;vol=1.58v;

vih=2.06v;vil=1.94v

ECL, PECL, lvpecl use Note: Different levels can not be directly driven. AC-coupled, resistor networks or special-purpose chips can be used in the intermediate conversion. All of the above three are shot with the output structure, must have a resistor pulled to a DC bias voltage. (such as multi-lvpecl for clocks: DC matching with 130 euro pull-up, while using 82 euro pull, ac matching with 82 euro pull, while using 130 euro drop.) But the two ways to work after the DC ping du at about 1.95V. )

The front level standard swing is relatively large, in order to reduce electromagnetic radiation, while improving the switching speed and the introduction of LVDS level standards.

LVDS: Low Voltage differential Signaling

Differential pair input and output, there is a constant current source 3.5-4ma, change the direction on the differential line to represent 0 and 1. The differential level of the ±350mv is converted to an external 100-Ohm matching resistor (and close to the receiving end on the differential line).

LVDS Use note: can reach more than 600M, PCB requirements are high, differential line requirements are strict and so on, preferably not more than 10mil (0.25mm). 100 ohms distance from the receiving end can not exceed 500mil, preferably controlled within 300mil.

TTL and CMOS differences

CMOS integrated circuit supply voltage can vary in a larger range, so the power supply requirements are not as stringent as the TTL IC. They can be compatible with TTL levels.

TTL ICS are current-controlled devices. Most TTL uses a 5V power supply.
1. Output high-level Uoh and output low-level UOL
uoh≥2.4v,uol≤0.4v
2. Enter the high and low input levels
uih≥2.0v,uil≤0.8v
Cmos
CMOS circuit is a voltage control device, the input resistance is very high, for the interference signal is very sensitive, so the unused input should not open, to the ground or power supply. The advantage of CMOS circuit is that the noise tolerance is wide and the static power consumption is very small.
1. Output high-level Uoh and output low-level UOL
Uoh≈vcc,uol≈gnd
2. Enter the high-level UOH and input low-level UOL
UIH≥0.7VCC,UIL≤0.2VCC (VCC is supply voltage, GND is ground)
As can be seen from the above:
In the same 5V supply voltage situation, the COMs circuit can directly drive the TTL, because the CMOS output high level is greater than 2.0V, the output low level is less than 0.8V, and the TTL circuit can not directly drive the CMOS circuit, TTL output High is greater than 2.4V, if it falls between the 2.4v~3.5v, the CMOS circuit can not detect high level, low level of less than 0.4V to meet the requirements, so the TTL circuit driver COMs circuit need to add a pull resistor. If there is a different voltage supply situation, can also be judged by the above Method (Vol is less than vil,voh to be greater than VIH, refers to a connection).
If the circuit appears 3.3V COMs circuit to drive 5V CMOS circuit, such as 3.3V MCU to drive 74HC, this situation has the following methods to solve, the simplest is to directly 74HC to 74HCT (74 series of input and output under the introduction) of the chip, because 3.3V CMOS can directly drive 5V TTL circuit, or add voltage conversion chip, there is the microcontroller I/O port is set to open leakage, and then add the pull resistor to 5V, in this case, according to the actual situation to adjust the size of the resistor to ensure that the signal rising along the time.

The upper and lower limits of the level are defined differently, and the CMOS has a larger noise-cancelling area.

The current drive capability is not the same, TTL generally provides 25 MA drive capability, while CMOS is generally around 10 ma.

The required current input size is also different, the general TTL needs about 2.5 Ma, CMOS hardly need current input.

Many devices are compatible with TTL and CMOS, datasheet will be described. If speed and performance are not considered, general devices can be interchanged. However, it is important to note that sometimes the load effect may cause the circuit to work abnormally, because some TTL circuits require the next level of input impedance as the load to function properly.

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TTL and CMOS level
1, TTL level (what is the TTL level):
Output high-level >2.4v, output low-level <0.4v. At room temperature, the general output high level is 3.5V, the output low is 0.2V. Minimum input high and Low: input high level >=2.0v, input low level <=0.8v, noise tolerance is 0.4V.

2, CMOS level:
1 Logic level voltage is close to the supply voltage, and 0 logic level is close to 0V. It also has a wide noise tolerance.

3, Level conversion circuit:
Because the TTL and COMs high and low values are not the same (TTL 5v<==>cmos 3.3v), so it is necessary to connect each other to the level of conversion: it is with two resistors to the electric pressure, there is no high-level things.

4, OC door, that is, collector open gate circuit, OD door, that is open-drain gate circuit, must external pull resistance and power to the switch level as high and low level. Otherwise, it is generally used only as a switching voltage and a large current load, so it is also called the drive Gate circuit.

5, TTL and COMs circuit comparison:
1) TTL circuit is a current control device, and CMOS circuit is a voltage control device.
2) The TTL circuit is fast, the transmission delay time is short (5-10ns), but the power consumption is large. The COMs circuit has a slow speed, long transmission delay (25-50ns), but low power consumption. The power consumption of the COMs circuit itself is related to the pulse frequency of the input signal, the higher the frequency, the hotter the chip set, which is the normal phenomenon.
3) Locking effect of COMs circuit:
COMs circuit because of the input too large current, the internal current sharply increased, unless the power is cut off, the current has been increasing. This effect is the locking effect. When the locking effect is generated, the internal current of the COMs can reach above 40mA, and it is easy to burn the chip.
Defensive measures: 1) at the input and output end of the clamp circuit, so that the input and output does not exceed the specified voltage.
2) The power input of the chip is coupled with a decoupling circuit to prevent a momentary high voltage at the VDD end.
3) A current-limiting resistor is added between the VDD and the external power supply, even if there is a large amperage that does not allow it to enter.
4) When the system is powered by several power supply, the switch should be in the following order: When open, first open the COMs Road power, and then turn on the input signal and load power supply, turn off the input signal and load power, and then turn off the power of the COMs circuit.

6, the use of COMs circuit precautions
1) COMs circuit voltage control device, its input total resistance is very large, the ability to capture interference signal is very strong. Therefore, do not leave the pin not dangling, to connect the pull-up resistor or pull-down resistor, give it a constant level.
2) input terminal low internal resistance signal source, to be in the input and signal source to series current limiting resistance, so that the input currents limit within 1mA.
3) When the long signal transmission line is connected, the matching resistor is terminated in the COMs circuit.
4) When the input is terminated with a large capacitor, the resistor should be indirectly protected at the input and capacitance. The resistance value of r=v0/1ma.v0 is the voltage on the external capacitor.
5) COMs input current of more than 1mA, it is possible to burn coms.

7, the TTL gate circuit input terminal load characteristics (input end with the special case of resistance processing):
1) is equivalent to the input termination high level when dangling. Because at this point it can be considered as the input terminating an infinitely large resistor.
2) Enter the low level after the 10K resistor is connected in series at the input end of the gate, and the input output is high rather than low. Because of the input load characteristics of the TTL gate circuit, only in the input termination of the series resistance is less than 910 kohm, the input of the low-level signal can be recognized by the gate Circuit, the series resistance is larger then the input has been high level. This must be noted. The COMs Gate Circuit doesn't have to be considered.

8. The TTL circuit has an open collector gate, and the MoS tube has an open-drain OD gate corresponding to the collector, and its output is called an open-drain output. OC door at the cutoff of the leakage current output, that is leakage current, why have leakage current? That's because when the transistor cutoff, its base current is approximately equal to 0, but is not really 0, through the transistor collector's current is not really 0, but about 0. And this is the leakage current.
Open-Drain output: The output of the OC Gate is the open-drain output, and the output of the Od gate is also the open-drain output. It can absorb very large currents, but cannot output the current outward. Therefore, in order to be able to input and output current, it should be used with the power and pull-up resistor together. OD gates are generally used as output buffers/drivers, level translators and meet the need to absorb large load currents.

9, what is called the totem pole, what is the difference between it and the open-drain circuit?
In the TTL IC, the output of the connected-to-pull transistor is called the Totem pole output, not the OC Gate. Because the TTL is a three-level switch, the totem pole is two three-stage push-pull connection. So push-pull is totem. General totem output, high level 400UA, low level 8MA

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CMOS devices do not have to be connected to high or low input terminals, because CMOS is a high input impedance device, the ideal state is no input current. If the input pin is not used, it is easy to sense interference signal, affect the logic of the chip operation, or even static accumulation of permanent breakdown of this input, resulting in chip failure.
In addition, only the 4000 series of CMOS devices can operate on a 15-volt power supply, 74HC, 74HCT and so can only operate on 5-volt power supply, now has a working in 3-volt and 2.5-volt power supply CMOS logic circuit chip.

CMOS power and TTL level:
CMOS logic level range is large, in the range of 3~15v, such as the 4000 series when 5V power supply, the output is higher than 4.6, the output below 0.05V is low. The input is high above 3.5V and the input is low below 1.5V.
And for TTL chip, the power supply range in 0~5v, common is 5V, such as 74 series 5V power supply, the output is high above 2.7V, the output is below 0.5V is low, the input is high above 2V, and below 0.8V is low level. Therefore, the CMOS circuit and the TTL circuit has a level conversion problem, so that the level of the field values can match.
Some concepts about logic levels:
To understand the content of a logic level, you first need to know the meanings of the following concepts:

Input high Level (VIH): To ensure that the input of the logic gate is the minimum allowable input high at high level, when the input level is higher than Vih, the input level is considered high.
Input low Level (VIL): To ensure that the input of the logic gate is lower than the maximum allowable input low level, when the input level is lower than Vil, the input level is considered low level.
Output High Level (VOH): To ensure that the output of the logic gate is the minimum value of the output level of the high normal, the output of the logic gate must be higher than the level of this Voh.
Output low Level (VOL): To ensure that the output of the logic gate is the maximum value of the output level at low level, the output of the logic gate must be lower than this Vol.
Threshold level (VT): The digital circuit chip has a thresholds level, that is, the circuit just barely able to flip the level of the action. It is an interface between Vil, Vih voltage value, for the CMOS circuit threshold level, is basically one-second of the supply voltage value, but to ensure stable output, you must require input high-level > Vih, Input Low-level <vil, and if the input level above the threshold value, In this area, the output of the circuit will be in an unstable state vil~vih.
For the general logic level, the relationship of the above parameters is as follows:
Voh > Vih > Vt > Vil > Vol
Ioh: The logic gate output is the load current at high level (for pull current).
Iol: The logic gate output is the load current at low level (for the sink current).
Iih: The logic gate input is the current at high power level (for the sink current).
Iil: The logic gate input is the current at low electrical level (for pull current).

The gate circuit output pole does not connect the load resistance in the integration unit and leads directly as the output end, this kind of door is called the Open door. The Open-circuit TTL, CMOS, ECL Gate is known as Open Collector (OC), open Drain (OD), open emitter (OE), and should be used to examine whether the pull-up resistor (OC, OD Gate) or pull-down resistor (OE gate), and the resistance value is appropriate. For an open collector (OC) door, the pull-up resistor value RL should meet the following conditions:
(1): RL < (VCC-VOH)/(N*IOH+M*IIH)
(2): RL > (vcc-vol)/(Iol+m*iil)
where N: The number of open gates of the line and M: the number of input ports driven.

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OC Gate, also known as collector open (open drain) and non-gate gate circuit, open Collector (open Drain).
Why is OC Gate introduced?
In practice, it is sometimes necessary to connect two or more two or more outputs with the non-gate to the same conductor, and the data (status level) on these and non-gates is conveyed by the same conductor. Therefore, a new and non-gate circuit--OC Gate is needed to achieve "line and logic".
OC doors are mainly used in 3 areas:

Implemented with or non-logic, used as a level shifter, used as a driver. As the collector of the output tube of the OC Gate Circuit is suspended, a pull-up resistor RP to the power supply VCC is required for use. The OC door uses a pull-up resistor to output the high level, and in order to increase the drive capability of the output pin, the selection principle of the pull-up resistor value should be large enough from the reduction of power dissipation and the ability of the chip to sink the current capacity; From ensuring sufficient drive current considerations should be small enough.
The logic function of "and" can be realized by direct interconnection of line and logic, i.e. two outputs (including more than two). In the bus transmission and other practical applications need a plurality of doors in parallel connection of the output terminal, and the general TTL gate output can not be directly connected to use, otherwise these gates of the output pipe between the low impedance of the formation of a large short-circuit current (sink current), and burn the device. On the hardware, the OC Gate or the Tri-State Gate (ST Gate) can be used to achieve this. With the OC door to achieve the line and should be at the same time the output port should be added a pull-up resistor.
Three-state Gate (St Gate) is mainly used in multiple gate output shared data bus, in order to avoid multiple gate output simultaneously occupy the data bus, these door enable signal (EN) Only one is allowed to have a valid level (such as high level), because the output of the tri-State gate is a push-pull low-impedance output, and do not need to pull So the switching speed is faster than the OC door, and the three-state gate is used as the output buffer.
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What is OC, OD?
Open collector Gate (open collector OC or open drain OD)
The open-drain is the meaning of an open-drain output, equivalent to an open collector (open-collector) output, which is an open collector (OC) output in the TTL. Generally used for wire or wire, and also for current drive.
Open-drain is the MoS tube, the open-collector is for the bipolar tube, in terms of usage is not very different.
The circuit of the open-drain form has several features:
A. Use the drive capability of external circuit to reduce the internal drive of IC. or drive a higher load than the chip supply voltage.
B. You can connect multiple open-drain pins to a single line. A pull-up resistor creates a "and logic" relationship without adding any devices. This is also the principle of I2c,smbus bus to determine the state of bus occupancy. If the output of the totem must be connected with a pull-up resistor. In the capacitive load, the falling delay is the transistor in the chip, the active drive, the speed is fast, the rising delay is the passive external resistor, the speed is slow. If the speed of high resistance is required to select small, power consumption will be large. Therefore, the choice of load resistance should take into account both power consumption and speed.
C. You can change the transmission level by changing the voltage of the pull-up power supply. For example, add a pull-up resistor to provide ttl/cmos level output, and so on.
D. The open-drain pin does not connect the external pull-up resistor, only the low level is output. In general, the open-drain is used to connect different levels of the device, matching the level of the.
The normal CMOS output stage is the upper and lower two tubes, the above pipe is removed is open-drain. The main purpose of this output is two: level shifting and line with.
Since the leakage stage is open, the back-stage circuit must be connected with a pull-up resistor, and the power supply voltage of the pull-up resistor determines the output level. This allows you to convert at any level.
Line and function is mainly used in the case of multiple circuits to the same signal to pull low operation, if this circuit does not want to pull low, the output high level, because the open-drain above the pipe is taken off, high level is by the external pull-up resistor to achieve. (While the normal CMOS output stage, if one output is high and the other one is low, it is equal to the power supply short circuit.) ）
Open-drain provides a flexible way to output, but it also has its weaknesses, which is the delay of the rising edge. Because the rising edge is the load charging through the external pull-up passive resistor, so when the resistance choice hour delay is small, but the power consumption is large, and the delay large power consumption is small. Therefore, if the delay is required, it is recommended to use a falling edge output

TTL level, CMOS level, 232/485 level, OC Gate, OD gate Basics