"Turn" depth analysis nandflash-physical structure and address transfer (take k9f2g08u0a as an example on the TQ2440 Development Board)

K9F2G08U0A is a nandflash of Samsung's total capacity of 256M, often used in handheld devices and other consumer electronics products. Or that sentence, the bottom will have to see datasheet, we are from its datasheet look.

This is the internal structure of k9f2g08u0a, specific parts of the introduction, not detailed introduction, want to know the words can refer to Wei Dongshan "Embedded Linux application Development complete manual."

Now take a look at the focus of the Nandflash storage unit's organizational structure, the K9F2G08U0A storage unit is organized as follows:

In conjunction with the above diagram, let us now analyze:

The Nandflash storage unit is made up of blocks, and the block is made up of page, and the data is stored on the page.

The total capacity of the k9f2g08u0a is 256M, as can be seen from the figure, it has a total of 2048 pieces, each piece has 64 pages, each page has (2k+64) Bytes. Each page is divided into the main area and spare area, 2K refers to the main area, 64 refers to the spare area.

2 k is the effective space on each page to hold data, 64 refers to each page attached to the space, it can not be used to store the data we write, it is mainly used to store ECC checksum bad block tag information data.

There is also a more important knowledge is the visit to Nandflash, you do not access it, then you certainly will not use it!

The first thing to understand is that the Nandflash is read and written in the smallest unit (page), erased by the smallest unit (block), that is, when we have given the starting position of the read, the read operation will start from that position and read continuously to the last of this page Byte (can include spare Field).

Before figuring out how to read and write Nandflash, there's still a preparation to do, and that's what we're going to tell Nandflash, where I'm going to read and write the data, and if we don't tell it the address, then it doesn't know what data we're reading. So how do we calculate the address we're going to pass in? Take an example to illustrate

Take k9f2g08u0a as an example, this NAND flash, a total of 2048 blocks, each block has 64 pages, each page is 2k+64 Bytes, assuming that we want to access the 1500th block in the page 25 of the The address at 1208 bytes, at which point we will first calculate the specific address:
Physical Address = Block size x block number + page size x page number + on-page address =1500x128k+25x2k+1208=0xbb8ccb8 (196660408), Next, let's see, How to translate this actual physical address into the format required by NAND Flash. Before interpreting the address composition, take a look at an introduction to the address cycle in its datasheet:

As can be seen, k9f2g08u0a is implemented in 5 cycles, because NAND flash reads and writes data in pages, and erases data in blocks. In this way, three types of addresses can be formed:
Column address:starting Address of the Register. Turn into Chinese as the column address, the address of the lower 8 bits, that is, the offset address in the page
Page Address: Pages addresses
Block Address: Blocks addresses

We know that each page of k9f2g08u0a has (2k+64) =2112byte,2112byte need 12bit to indicate, for 2112byte series of NAND, this 2112byte is divided into 1st half Page Register and 2nd Half Page Register, the respective access is selected by the address pointer command, a[11:0] is the so-called column address, which is not required for the erase operation because it is erased in blocks. 64 pages need 6bit to represent, Occupy A[17:12], that is, the page's relative address within the block, that is, which page to determine. A11 This address is used to set the 2048byte 1st half page or 2nd half page,0 indicates that the 1st,1 is 2nd. The address of the block is represented by a bit above A18, which is where it is located. With A[0:28] This 29-bit, you can k9f2g08u0a this 256M of data storage space to all access.

2 of the 29-time parties are 2gbit,256mbyte=2gbit.

The address of the NAND Flash is expressed as: Block address| Page Address in block| The column address routing order is column Address,page Address,block addresses.
Since the address can only be passed on i/o[7:0], it must be done in a shift manner. Take k9f2g08u0a as an example:
The 1th step is to pass the column address, which is nand_addr[7:0], which can be passed to i/o[7:0] without a shift.
The 2nd step is to move the nand_addr right 8 bits and Nand_addr[11:8] to i/o[7:0];
The 3rd step is to put nand_addr[19:12] on I/O;
The 4th step needs to put nand_addr[27:20] on the I/O;

The 5th step needs to put nand_addr[28] on the I/O;
Therefore, the entire address delivery process takes 5 steps to complete, namely 5-step addressing. If the capacity of NAND Flash is below 32MB (256Mbit), then the block adress the highest bit only to bit24, so addressing requires only 3 steps.

After simply explaining the address composition, it is easy to analyze the address in the example above:
0XBB8CCB8 = 00001011 1011 1000 1100 1100 1011 1000, each assigned to 5 address cycles is:

b b 8 c c B 8

First cycle: A[0:7] that is B8

Second cycle: A[8:11] take four bits 1100, add 4 bit 0, that is 0000 1100 is 0C

Third cycle: a[12:19] take eight bits 1000 1100 that is 8 C

Fourth cycle: a[20:27] take eight bits 1011 1011 that is BB

Fifth cycle: a[28] Take a bit 0, eight bits is 0000 0000 is 00

Back to the analysis, Nandflash received the first two cycles of address a[0:11] that is 0CB8, that is 1100 1011 1000, analysis: a[10:0]= 100 1011 1000=1208, indicating a 1208th byte

After receiving the last three cycles, namely 0000 0000 1011 1011 1100,A[16:11]=011001=25, the 25th page

0000 0000 1011 1011 100 after processing is 0101 1101 1100 = 1500, representing the 1500th block

Original address: http://blog.csdn.net/it_114/article/details/6258509

"Turn" depth analysis nandflash-physical structure and address transfer (take k9f2g08u0a as an example on the TQ2440 Development Board)