Turn: DDR3 detailed (Take micron MT41J128M8 1Gb DDR3 SDRAM as an example)

Reprinted from: http://blog.csdn.net/shanghaiqianlun/article/details/6976804

Shanghaiqianlun's Column

1. Structural block Diagram:

2. Pin function Description

Pin symbol	Type	Describe
A0-a9,a10/ap,a11,a12/bc#,a13	Input	Address input. Provide a line address for the Activate command, and a column address for the Read/write command and an automatic pre-charge bit (A10) to select a location from a bank's memory array. The A10 is sampled during the Precharge command to determine whether the precharge should be at a bank:a10 low, the bank is chosen by ba[2:0], or A10 for high, to all banks. During the load mode command, the address input provides an opcode. The reference for address input is VREFCA. A12/bc#: When the Mode register (MR) is enabled, A12 is sampled during the read and write commands to determine whether burst chop (on-the-fly) will be executed (High=bl8 execute burst Chop), Or LOW-BC4 do not perform burst chop.
Ba0,ba1,ba2	Input	Bank address input. The define activate, READ, write, or Precharge commands are operated on that bank. BA[2:0] defines which mode (MR0, MR1, MR2) is loaded during the load Mode command, ba[2:0] reference is VREFCA
ck,ck#	Input	Clock. The differential clock input, all control and address input signals are sampled at the intersection of the CK rising edge and the ck#, and the output data is selected (DQS, dqs#) reference to the intersection of CK and ck#.
CKE	Input	Clock Enable. Enable (high) and prohibit (low) internal circuits and clocks on DRAM. Determined by the DDR3 SDRAM configuration and operation mode a particular circuit is enabled and forbidden. CKE is low, provides precharge power-down and self refresh operations (all banks are idle), or effectively power down (in any bank row). Cke and power-down status of entry and exit and self-flushing into sync. Cke with self-flushing exits asynchronously, input buffer (except CK, ck#, reset#, and ODT) is forbidden during power-down. The input buffer (except Cke and reset#) is forbidden during self refresh. The reference of Cke is VREFCA.
cs#	Input	Film Selection. Enable (low) and prohibit (high) command decoding, when the cs# is high, all the commands are blocked, cs# provides the rank selection function of the multi-rank system, cs# is part of the command code, cs# reference is VREFCA.
Dm	Input	Data entry masking. DM is the input shielding signal to write data, during writing, when the DM signal accompanying the input data is sampled as high, the input data is masked. Although the DM is only used as an input pin, the DM load is designed to match the DQ and dqs foot loads. The reference of DM is VREFCA. DM is optional as Tdqs
ODT	Input	On-chip terminal enable. The ODT enables (high) and disables (low) on-chip termination resistors. When normal operation is enabled, the ODT is only valid for the following pins: dq[7:0],dqs,dqs# and DM. If disabled by the load Mode command, the ODT input is ignored. The ODT reference is VREFCA
ras#,cas#,we#	Input	command input, these three signals, together with cs#, define a command whose reference is VREFCA
reset#	Input	The reset, low-effective, reference is VSS, and the reset assertion is asynchronous.
Dq0-dq7	/ o	Data input/output. Bidirectional data, dq[7:0] reference VREFDQ
dqs,dqs#	/ o	Data selection. The output is read, and the edges are aligned with the read data. Write is input, center is aligned with write data.
tdqs,tdqs#	Output	Terminal data selection. When the TDQS is enabled, the DM prohibits, TDQS and TDDS provide the terminating resistor.
Vdd	Supply	Supply voltage, 1.5v+/-0.075v
VDDQ	Supply	DQ power supply, 1.5v+/-0.075v. Isolation on the chip to reduce noise
Vrefca	Supply	The reference voltage of the control, command, and address. VREFCA must maintain the specified voltage at all times (including self-flushing)
Vrefdq	Supply	The reference voltage of the data. VREFDQ must maintain the specified voltage at all times (except self-flushing)
Vss	Supply	To
Vssq	Supply	DQ, in order to reduce noise, the chip is isolated.
ZQ	Reference	External reference for output drive calibration. This foot should connect the 240ohm resistor to the VSSQ

3. State diagram:

ACT = ACTIVATE PREA = precharge all SRX = self-Refresh Eject

MPR = multi-use register READ = Rd,rds4,rds8 write=wr,wrs4,wrs8

mrs= Mode register set READ ap=rdap,rdaps4,rdaps8 write=wrap,wraps4,wraps8

Pde= power down into Ref=refresh zqcl=zq LONG calibration

Pdx= power off launches reset= start-up reset process Zacs=za short calibtation

Pre= pre-charge sre= self-refresh entry

4. Basic functions

The DDR3 SDRAM is a high-speed dynamic random access memory with 8 banks in its internal configuration. The DDR3 SDRAM uses a 8n prefetch structure for high-speed operation. The 8n prefetch structure is combined with the interface to complete the transmission of two data words per clock on the I/O pin. DDR3 SDRAM a single read or write operation consists of two parts: one is the 8n bit width four clock data transmission in the internal DRAM core, the other is two corresponding n-bit wide, half clock cycle data transmission on the I/O foot.

The read and write operation of DDR3 SDRAM is a directional burst operation, starting from a selected position, the burst length is 8 or a chopped burst mode with the length of the programming sequence of 4. The operation starts with the active command, followed by a read/write command. The active command concurrently contains the address bits to select the Bank and row address (BA0-BA2 Select Bank, A0-A15 select Row). The Read/write command concurrently contains the starting column address with the burst operation and determines whether to publish the automatic pre-Charge command (via A10) and select BC4 or BL8 mode (via A12) (if the mode register is enabled).

Before normal operation, DDR3 SDRAM must be power-up and initialized in a pre-defined manner.

Turn: DDR3 detailed (Take micron MT41J128M8 1Gb DDR3 SDRAM as an example)