"Turn" STM32 Timer output comparison mode doubts

The relationship between OCX and Ocxref and CCXP

Beginner STM32, I this place card for a long time, now finally some understand, now put my understanding write down with you share, if there is wrong place, also please point out.

Ocxref is a reference signal, and the Agreement:

Ocxref=1, called Ocxref effective. Conversely, ocxref=0, called Ocxref Invalid;

The ' 1 ' level (high level) is called the active level of the ocxref, and the ' 0 ' level (low) is called the invalid level of the ocxref.

--According to the reference manual: The output stage generates an intermediate waveform which are then used for Reference:ocxref (active high). The polarity acts at the end of the chain.

(translation) The output phase produces an intermediate waveform ocxref ( highly effective ) as a reference. The polarity of the output signal is reflected at the end of the signal chain.

Now explain the relationship between several nouns:

Then to understand several modes of the output comparison (PWM mode is a special case of the output comparison mode)

View the oc1m domain of the TIMX_CCMR1 register, as defined below (excerpt from the latest version of the reference manual)

Translate as follows:

000: Freeze-The comparison between the content in the output comparison register TIMX_CCR1 and the content in the counter timx_cnt has no effect on the output. (this mode is used for generation of time bases)

001: When matching, set channel 1 to the active level . When the contents of the Counter timx_cnt match the contents of the Capture/compare Register 1 (TIMX_CCR1), force the high oc1ref signal to be pulled.

010: When matching, set channel 1 to an invalid level . When the contents of the Counter timx_cnt match the contents of the Capture/compare Register 1 (TIMX_CCR1), the low oc1ref signal is forcibly pulled .

011: Flip--When the timx_cnt= TIMX_CCR1, the oc1ref signal is reversed.

: force Invalid level--forcibly pull down the oc1ref signal .

101: Force Active level--forcibly pull the high oc1ref signal .

110:PWM mode in the Count mode, as long as the timx_cnt< TIMX_CCR1, Channel 1 is valid , the inverse is not valid . In the down Count mode, if Timx_cnt> TIMX_CCR1, Channel 1 is not valid (oc1ref=0 ) and vice versa (oc1ref=1).

110:PWM mode 2--up in the Count mode, as long as timx_cnt< TIMX_CCR1, Channel 1 is not valid, vice versa. In the down Count mode, as long as Timx_cnt> TIMX_CCR1, Channel 1 is valid and the inverse is not valid .

I marked the reference to a valid, ineffective place in red. It is not difficult to find that the effective and invalid respectively correspond to oc1ref=1 and oc1ref=0. This is the result of our earlier agreement.

As a result, the effect of output comparisons in different modes on the OC1REF signal is already clear, but the final output signal is OC1, not oc1ref. And there is a word in front (the polarity of the output signal is reflected in the end of the signal chain ) has not yet been explained.

What is the secret between Oc1ref and OC1? Let's take a look at the following diagram:

Obviously, we only care about the signal in the red circle and the register bit in the box and how the signal spreads between them.

The oc1ref starts with the output mode controller, which is divided into two ways, one to the main mode controller (to the master), where we do not care about its whereabouts, we are concerned about the following, The following road into the two-way switch before it was split between the original signal, all the way is the original signal of the non. obviously the cc1p bit in the timx_ccer is used to control the switch, and the CC1E bit controls the entire signal chain's continuity .

When Cc1p=0 (cc1e=1):

When Cc1p=1 (cc1e=1):

 

Obviously, the relationship between OC1 and Oc1ref is only affected by cc1p (cc1e=1)

The reference manual, however, describes the CC1P bit as follows:

Cc1p=0: OC1 High Active

Cc1p=1: OC1 Low Active

According to the noun explanation at the beginning of this article, we can understand:

Cc1p=0: OC1 active level is high

Cc1p=1: OC1 Active level is low

This is confusing, what is the meaning of this active high and low level effective?

We analyze from the beginning (the output of the entire process Cc1e=1,oc1 is allowed):

1 Assuming that the Oc1ref is valid (oc1ref=1), then the signal from the entire signal chain from Oc1ref to OC1 is a valid signal, and we call the OC1 output an effective signal .

is the valid signal high or low?

This is determined by cc1p:

2 Assuming that the Oc1ref is invalid (oc1ref=0), then the signal from the entire signal chain from Oc1ref to OC1 is an invalid signal, and we call the OC1 output an invalid signal .

The high and low levels of the invalid signal are also determined by the cc1p:

Use a table to summarize the above process:

Oc1ref	cc1p	Function	OC1	Describe
0	0	OC1 High Active	0 (Low level)	Invalid
	1	OC1 Low Active	1 (High level)	Invalid
1	0	OC1 High Active	1 (High level)	Effective
	1	OC1 Low Active	0 (Low level)	Effective

Obviously, theOc1ref determines whether the OC1 output level is valid, and cc1p determines the polarity of the active level .

We pulled out the last four columns of the table:

cc1p	Function	OC1	Describe
0	OC1 High Active	0 (Low level)	Invalid
1	OC1 Low Active	1 (High level)	Invalid
0	OC1 High Active	1 (High level)	Effective
1	OC1 Low Active	0 (Low level)	Effective

We combine the table in columns 1 and 2

cc1p	Function	OC1	Describe
0	OC1 High Active	0 (Low level)	Invalid
	OC1 High Active	1 (High level)	Effective
1	OC1 Low Active	0 (Low level)	Effective
	OC1 Low Active	1 (High level)	Invalid

It is now clear that the cc1p control of the effective polarity of OC1 can be clearly seen from the table above. That is, the polarity of theOC1 is only valid (green part) only if it is consistent with the effective polarity specified by the cc1p. This explains the phrase "the polarity of the output signal is reflected at the end of the signal chain ".

But the chain is not over yet, and there is a cc1e. Of course, it is just a OC1 output enable bit.

But careful you may find that the reference manual has such a description of the CC1E bit:

OCx = ocxref + polarity

This equation tells us about the relationship between OCX and Ocxref and polarity (polarity, that is, CCXP bit).

We have mentioned their relationship, which is divided into two cases (Cc1p=0 and cc1p=1), which helps us to sum up the relationship above. How did you get the formula?

Recall the semi-adder in the digital circuit (that is, the addition of non-rounding), the truth table is as follows:

Ocxref	Polarity	Ocx
0 (invalid)	0 (Highly effective)	0 (invalid)
0 (invalid)	1 (Low Effective)	1 (invalid)
1 (valid)	0 (Highly effective)	1 (valid)
1 (valid)	1 (Low Effective)	0 (valid)

We write the logical function (written in the yellow section):

Note: The preceding "+" sign indicates that the half-plus operation (without carrying the addition) is actually a logical "XOR".

"Turn" STM32 Timer output comparison mode doubts