[Turn] What is a tri-state gate/high-impedance state? And the application of three-state gate

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What is tri-State gate/high-impedance state? And the application of three-state gate

What is a state gate?

Three-state gate, refers to the output of the logic gate in addition to the high and low level of the two states, there is a third state-impedance state of the gate circuit. The high impedance is equivalent to the partition state (large resistance, equivalent to open circuit). The Tri-State Gate has an en control enable to control the gate Circuit's continuity. Devices that can have these three states are called Tri-State (gate, bus,......).
The computer is 1 and 0 means, not two kinds of logic, but, sometimes, it is not enough, for example, he is not rich, but he is not necessarily poor ah, she is not beautiful, but not necessarily ugly ah, in the middle of these two extremes, with that is neither + nor--the middle state of the expression, called high impedance state. High level, the low level can be pulled up and pulled down by the internal circuit. When the high impedance state, the pin to ground resistance is infinite, at this time the reading pin can read the actual level value. One of the important functions of high-impedance states is that I/O (input/output) ports are read into the external level at input.

The high-impedance state is equivalent to the gate and the circuit to which it is connected is in a disconnected state. (Because you cannot disconnect it in the actual circuit, set such a state so that it is in a disconnected state.) The Tri-State gate is an output stage that extends the logic function and is also a control switch. It is mainly used for bus connections, because the bus only allows only one user at a time. Typically, multiple devices are connected to the data bus, and each device is oe/ce via a signal such as a. If the device is not selected, it is in high impedance state, the equivalent of not connected to the bus, does not affect the work of other devices.
If your device port is to be hung on a bus, you must pass the tri-State buffer. Because only one port can be output on one bus at a time, other ports must be in a high impedance state while the data of this output port can be entered. So you also need to have a bus control management, to which port to access, the port of the three-state buffer can be transferred to the output state, this is a typical three-state gate application. If there are not more than two output devices on-line, of course, less than three-state gate, and the line or logic is another matter.

Three-state and non-gate structure
three-state and non-gate output In addition to the general and non-gate of the two states, that is, the output resistance of a small high and low state, but also has a high output resistance of the third State, known as High impedance state , also known as the Forbidden State .
A simple TSL gate circuit 4.4.8 (a) shows that figure (B) is its logical symbol. Where CS is the chip-selected signal input,a,B is the data input terminal.

Fig. 4.4.83-State and non-gate circuits (A) circuit diagram (B) logic symbols
When CS= 1 o'clock, the T5 in the TSL Gate circuit is in an inverted amplification state, the T6 is saturated and T7 is cut off, i.e. its collector is equivalent to an open circuit. The logical relationship between output and input is the same as the normal and non-gate. This state becomes the working state of the TSL. But when CS= 0 o'clock, the T7 is on, so that the base of T4 is clamped to the low level. At the same time, the low-level signal is sent to the input of T1, forcing T2 and T3 to expire. So the T3 and T4 are cut off, the output of the gate L open, neither low nor high, this is the third working state. Thus, when CS is high, the output signal of the TSL gate is sent to the bus, and when CS is low, the output of the gate is disconnected from the data bus, at which time the state of the data bus is determined by the output of the other gate circuits.  

What do you mean high-impedance states
High-impedance state this is a common language in a digital circuit, refers to the circuit of an output state, is not high or low level, if the higher impedance state and then enter the next level of the circuit, the lower circuit has no effect, and the same, if the multimeter can be measured by the high level may also be low level, It depends on what is attached to the back.

The essence of the high-impedance state: When the circuit is analyzed, it can be opened. You can think of it as a very large output (input) resistor. His limits can be thought of as dangling. That is, the theoretical high impedance is not suspended, it is to the ground or to the power of a large state of resistance. The actual application is the same as the pin dangling.
(When the output of the gate circuit slide on the slide cutoff, the output is high, the reverse is low level, if the upper slide and lower slide are cut off, the output is equivalent to floating (no current flow), its level with the external level, that is, the gate circuit to give up control of the output terminal circuit)

Typical applications:
1, on the structure of the bus connection. A plurality of devices are hung on the bus, and the device is connected in high-impedance form on the bus. This frees the bus automatically when the device does not occupy the bus (discarding the use of the bus) to facilitate access to the bus by other devices.
2, most of the single-chip microcomputer I/O can be set as high resistance input, such as Ling Yang, AVR and so on. High-impedance input (similar to CMOS input impedance) can be considered as an infinite input resistor, I/O is considered to have a minimal impact on the front stage, and does not generate current (no attenuation), and to a certain extent, it also increases the ability of the chip to resist voltage shock.

[Turn] What is a tri-state gate/high-impedance state? And the application of three-state gate