Tvp5150 low-power video decoding module

TVP5150 low-power video decoding module

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Source: China Power Grid Author: Jiang Chenming, Shi Xiaojun

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0 Introduction With the rapid increase in the demand for portable multimedia terminals, the demand for low chip power consumption in video decoding and other aspects is also increasing. Therefore, only by converting analog video signals into digital signals that comply with the ITU-R BT.656 standard can FPGA or DSP or even PC be used for Signal Processing conveniently. This module uses TI's ultra-low power TVP5150 chip to decode video signal A/D. It is controlled by A single-chip microcomputer through I2C bus and reserved address data and other interfaces, used for module verification and subsequent digital signal processing. 1 module hardware structure 1.1 Basic System Structure The overall system architecture is shown in Figure 1. TVP5150 is a high-performance video decoder that supports formats such as NTSC, PAL, and SECAM with ultra-low power consumption. It consumes only 115 mW of power during normal operation, it has a super-small package (32-pin TQFP), so it is very suitable for portable, batch large, high-quality and high-performance video products. It can receive two CVBS or one S-Video signal. The internal register can be set through MCU I2C bus, can output 8-bit ITU-R BT.656 signal (embedded synchronous signal), and 8-bit ITU-R BT.601 signal (synchronous signal separation, single pin output ). The single-chip microcomputer uses TI's MSP430F2013, Which is ultra-low power. It has 2 kB + 256 B Flash memory and 128 B RAM, and 14-foot ultra-small package (TSSOP ). Its power consumption is 1/5 of the average single-chip microcomputer, especially suitable for handheld devices, in 1.8 V ~ 3.6 V voltage, 1 MHz clock, the power consumption current is 0.1 μA ~ 400 μA (varies depending on the working mode ). The single-chip microcomputer is connected to the serial port through MAX3232. The PC program the single-chip microcomputer online through the serial port, which facilitates timely modification of the single-chip microcomputer program. Set by the PC and adjust the internal registers of TVP5150 at any time to control its working status and output signals. MCU reserved control port to increase the scalability of this module. 74HC16245 bus controller is used to improve the load driving capability of the output signal of this module. It is an optional part and can pass through the signal as needed to reduce the power consumption of the module. If multiple modules work together, the MCU can control 74HC16245 and coordinate the signal output of each module. The verification module is mainly composed of SAA7121 Video Encoding Chip, which can encode the 8-bit ITU-R BT.656 or ITU-R BT.601 input signal into CVBS signal or S-Video signal output. If the TVP5150 decoding module works normally, the verification module can obtain analog video signals, and the receiver display device can obtain input images. 1.2 system hardware design Diagram 2 of TVP5150 chip application. The chip uses a 14.318 18 MHz Crystal Oscillator with a digital and analog input voltage of 1.8 V and an I/O port voltage of 3.3 V. The signal input includes two channels, namely, megaand CH2, both of which are designed for impedance matching, prevent reflection on the input signal. YOUT [0: 7] outputs eight YCbCr signals. The hidden signals can be output by HSYNC and VSYNC on individual pins, or embedded in these eight signals. The PCLK/SCLK pin clock signal can output two frequencies: 13.5 MHz and 27 MHz. 2 Module Program Composition This module is mainly composed of PC and single-chip microcomputer serial communication program and single-chip microcomputer and TVP5150 I2C control program. 2.1 PC and single chip microcomputer serial port communication program The communication protocols between PCs and single-chip microcomputer are shown in table 1. Note: The quotation marks are transmitted Data headers for MCU identification and processing; Addr is the address; Data is the Data. This program is designed in the dephi7.0 development environment. The configuration file is in the txt format. It can read and save the configuration file and perform simple processing on the configuration file in the configuration table, the register information in the configuration file can be sent to the microcontroller through the serial port, and the register information sent by the microcontroller can be read. The program is divided into two layers: Front-End Interface processing, back-end data processing, and function processing. The front-end is only responsible for interface settings and actions. All data in the table is processed in the back-end. Use the SPcomm serial communication control to perform serial communication. Define the Sendlist and Revlist classes, store all allowed sending items to Sendlist, and then send them through the serial port, and store the data sent by the MCU to Revlist. Then, compare Sendlist and Revlist. If they are the same, they are stored and displayed in the table. Otherwise, an error is returned. Each register item sent has a certain delay for MCU processing. The software has a timeout setting. If the MCU cannot receive the reply data after sending the message for 5 s, it is deemed as a timeout error. The procedure 3 is shown in. 2.2 MCU Program The Single-Chip Microcomputer Program provides two functions: Serial Communication and I2C bus control. Figure 4 shows the I2C sequence. The I2C bus is a serial bus consisting of a data cable SDA and a clock line SCL. It can send and receive data. The I2C bus has the following three types of signals during data transmission: A) Start signal ). In high-power mode, SDA switches from high to low and starts to transmit data. B) end signal (Stop ). In high-power mode, SDA changes from low-level to high-level and ends data transmission. C) response signal (AcK ). After receiving 8-bit data, the IC that receives the data sends a specific low-level pulse to the IC that sends the data, indicating that the data has been received. When transmitting data, the I2C bus must ensure that the data on the SDA is stable at high-power-on times of the SCL; otherwise, the data is regarded as the start or end signal. The program in the single-chip microcomputer transmits data with the PC according to the communication protocol, and then identifies the data header and processes the data separately according to the protocol. The internal registers of TVP5150 are read and written through the I2C bus. The single-chip microcomputer Communication and receiving main program is written in C language. It receives PC data through serial port interruption and determines whether the received data is a data header or valid data. When receiving the data header R, send back the PC r, then read the data in the address register TVP5150 from the next one byte address and send it back to the PC through the serial port. If the frame header is W, send back to PC w, and cache the data of the next two bytes, 1st bytes are the TVP5150 Register address, and 2nd are the data written into this register. The write operation is completed through the I2C bus, and the data in the register is read and sent back to the PC through the serial port for software verification on the PC end. 3 main Video Signals 3.1 output signal The module decodes the analog video signal into a digital video signal conforming to the ITU-R BT.656 standard, and outputs 8-bit Y: Cb: Cr = digital signal. The synchronous signal is embedded in the serial output in the data stream. It can also be output along with the data stream separately. Figure 5 shows a complete frame of data, divided into two parity fields, 23 ~ The fifth row is an even number of fields. The value ranges from 311 to 366 ~ The first row contains an odd number of fields, and the rest are field control signals or invalid data. FID indicates the parity field signal, and the field synchronization signal (VSYNC) drops along the hop. VBLK is a hidden field signal, which is effective at the High Level. You can set the TVP5150 register to change its length and control the output of valid image data, because effective video data is output during the low level of the VBLK signal. The data structure of each row is 6. The first 288 bytes of each line are the row control signal, and the first 4 bytes are the EAV (effective video end) signal, followed by 280 fixed-filling data, the last four bytes are the SAV (effective video start) signal. The SAV signal and EAV signal have three bytes of leading: FF, FF, and 00. The last one byte XY indicates that the row is located at the position of the entire data frame and how to distinguish the SAV and EAV signals. The meanings of XY are 7. In the figure, the highest bit is fixed data 1, F = 0 indicates an even number of fields, F = 1 indicates an odd number of fields, and V = 0 indicates the behavior of valid video data, V = 1 indicates that the row does not have valid video data. H = 0 indicates the SAV signal, H = 1 indicates the EAV signal, and P3 ~ P0 is the protection signal, which is calculated and generated by F, V, and H signals. 3.2 AVID Interception The AVID signal is a proprietary signal generated by TVP5150. It is a valid video data indicator signal. The AVID output data is invalid when it is low, and the AVID is valid when it is high. This provides a method to control the bandwidth of TVP5150 output video data. You can set the Register to control the start time and end time of the AVID and control the start time of the VBLK signal at the same time. Then, some parts of the output can be captured from a frame of image, as shown in figure 8. 4 Conclusion The debugging of this module is combined with the SAA7121 video encoding module. The analog video signal output by the video signal generator is decoded by this module and converted to a digital video signal. Then, the SAA7121 module converts the analog video signal into a display device. If the module runs normally, the input screen corresponding to the device is displayed. In step 1, input the signals of each RGB monochrome video and observe the output video and the synchronization signals through the oscilloscope. After the timing is normal, the display device is connected through the SAAT121 module. After obtaining the correct image, the module inputs the CVBS signal from the dvdserver. If the display device obtains the normal image, the debugging is basically complete. The main task of debugging is to correctly set the internal registers of TVP5150 and the effect of the changes on the output signals. If 74HC16245 is enabled, the total power consumption of this experiment module is about 200 mW. If 74HC16245 is disabled, the power consumption can be controlled at about 130 mW. It can be seen that the power consumption parameter of the video decoding module is very low. If the single chip microcomputer program is optimized, the power consumption can be further reduced. This module decodes the analog composite video signal into a digital video signal output conforming to the ITU-RBT.656 standard. It facilitates the use of FPGA and DSP for digital video signal output, and facilitates the use of FPGA, DSP, and other digital video images to interwork, making it easy to use FPGA and other digital video force images to interwork, resolution conversion and even MPEG encoding.