Two--(1)

Chapter II Protection Mode 80386 profile "01:30" 8086 addressing space 1M "01:32" 80286 addressing space 16M "01:36" 80386 addressing space 4g control register (eflags) "01:57" EFL AGS is used to instruct the microprocessor "02:41" TF (Trap flag) To activate the debug function on the microprocessor chip.    If 1, debugging is allowed, and if 0, debugging is forbidden. "03:05" IF (interrupt flag) controls the input operation of the INTR pin.        For the 1,intr pin is allowed; for the 0,intr pin is forbidden. ZC: What are you allowed and forbidden to do?    Input?    "03:20" DF (direction sign) ZC: Remember in the past, please is this sign it? "03:37" IOPL: The priority of the input and output. This flag is used to protect the IO device from selecting a priority when operating in protected mode. If the priority of the current task is higher than the IOPL IO instruction, it will execute smoothly (sequential execution). If the IOPL is lower than the priority of the current task (ZC: is that reversed?)        Here and in front is a meaning AH) generates an interrupt that causes the execution program to be suspended.    00/01/10/11 "04:18" ==> highest priority; ==> lowest priority.    "04:35" NT (nested flag): In protected mode, the current execution task is nested in another task, and this flag is set.    "04:58" RF: is used in conjunction with the Debug register to control the execution of the program after the next instruction. "05:15" VM: The mode used to select the virtual operation in the protected mode system.    The virtual mode system allows multiple 1M long DOS storage partitions to coexist in the memory system, allowing the system to execute multiple DOS programs.    ZC: About the meaning of these signs, looks like an article on the Internet similar content, see "... \ page \ Description of the multi-function register" inside the contents of the page saved. "05:45" Home Watch control register CR0, CR1, CR2, CR3 "05:55" CR1: No use in 80386, it is reserved for subsequent products. (ZC: Does it use it now?)            "06:10" CR2: Save the line Address "06:20" of the last page visited before the page failure is interrupted CR3: Saves the base address of the page directory. Left 20-bit (high 20-bit) is always valid, and the low 12 bits are 0. The low 12 bits of the CR3 together with the other bits to determine the starting address of a 4K long page. (ZC: What is the "other bit" here?)            "06:52" mainly look at the cr0:cr0 in a number of specific control bits. "07:01" PG (31st bit): A value of 1 ==> Select the linear address to physical address conversion (that is, the paging mechanism is turned on) "07:28" ET (4th bit): A value of 0 ==> select 81287 coprocessor; value 1 ==> Select 8038 7 co-processor. "07:45" The reason this bit, is ∵80386 just started out when there is no 80387 (ZC: coprocessor), in most systems, ET is set (setting a value of 1) indicates that the system does not have 80387 "08:08" TS (3rd bit): Indicates that the system has switched bits (Z C: It's not very clear to hear).            A value of 1 ==> coprocessor instruction causes an interrupt of type 7, and type 7 is the coprocessor does not exist. "08:30" EM (2nd bit): A value of 1 ==> allows each ESC instruction to cause Type 7 interrupts (ZC: There is an ESC directive?). )。            We usually use this interrupt software to simulate the functionality under the Coprocessor instructions, which can reduce the cost of the system, but it usually takes at least 100 times times for the coprocessor instructions to execute the simulation. "09:05" MP (1th bit): A value of 1 ==> indicates that the system has a coprocessor "09:12" PE (No. 0 bit): A value of 1 ==> Select the protection mode, turn on the protection mode of the segment level, the value of 0 ==> into real mode. In 80286, the bit can only be set, 86,286 hardware reset to return to Real mode (ZC: What is "hardware Reset"?) )。        80386 There is no such limit. ZC: Control register CR0 in the PE, PG bit control the segmentation mechanism and paging mechanism, it is not very clear, as long as they are set, it is forced to open the segmentation/paging mechanism? Can I not use the segmentation/paging mechanism when they are placed? How does this really control it? Can I use segmented/paged-related registers only when they are set? "09:53" "Real mode register addressing 1, segment and offset 2, default segment and offset register protection mode addressing 1, select child and descriptor" 10:41 "protection mode and real mode addressing differences: Protected mode segment address no longer looks like real modeThat is provided by the segment register, which contains a selector (either a segment selector or a selector) in the segment register where the segment address was originally stored. Select the child to use to select a descriptor within the descriptor table. Descriptor describes the location/length of the memory segment/access permissions. "11:20" because the segment register and the offset address are still used to access the memory, both the protection mode instruction and the real mode instruction are identical. "11:42" The difference between the two modes is that the microprocessor accesses the memory segment to interpret the segment register differently (ZC: So you need to look at CR0 's pe/pg bit to decide which way to use). Another difference is that in protected mode, a 32-bit number can be used instead of a 16-bit, 32-bit offset address microprocessor to access data in segments up to 4G.    "12:22" "1, select Child and Descriptor" in the segment register, select one of the 8,192 descriptors from either of the two descriptor list (GDT Global descriptor or LDT local descriptor).    "12:47" Descriptor: It is used to describe the location/length/access rights of the segment of the memory.    The segment register still selects a memory segment, but it is no longer directly selected as the real mode, but as an indirect choice.    The "13:26" GDT Global descriptor contains the segment definitions that apply to all programs.    "13:33" The LDT local descriptor descriptor usually applies only to the unique application.    "13:41" can refer to the global descriptor as a system descriptor, and the local descriptor descriptor is called the application descriptor. "13:49" Each descriptor has a maximum of 8,192.        ∴ the application can have up to 16,384 descriptors at any time. How is the relationship between zc:16384 and 8192 determined?         (16384/8192 = 2) zc:16384 and 8192 How are these two numbers obtained?        What's the relationship with 4G (4194304)? zc:4194304/8192 = zc:4194304/16384 = 256 "14:00" ∵ A descriptor describes a memory segment, which allows to describe a segment of up to 16,384 memory for each application "14:20 "The base address portion of the descriptor, just the starting position of the memory segment. The 80386 and higher microprocessors use a 32-bit base address that allows the segment to start at any place in the 4G memory.    The segment bounds contain the largest offset address in the segment. "15:00" 80386 and higher-model microprocessors can access length: 1 bytes ~A memory segment between 1M bytes or 4K bytes ~4g (ZC: bytes). Why is there a two-paragraph? Cause: There is a "G" bit in the descriptor, and this bit represents the granularity. The "G" bit value is 1 o'clock, and its growth ratio is in 4 K-bit units, ∴ it is 4K bytes ~4g (ZC: bytes).    The "G" bit value is 1 o'clock, in units of byte-bit growth, ∴ is between 1 bytes ~1m bytes. "16:03" "AVL" bit: Indicates that the segment is valid/invalid.    A value of 1 ==> indicates that the segment is valid, and a value of 0 ==> indicates that the segment is invalid. The length of the "16:30" Descriptor is 8 bytes (ZC: No wonder there are two 0-32-bit) "16:46" "d/b" bits: The D-bit indicates whether the data in protected mode or in real mode is specified to access the register or memory. If the d==0: instruction is compatible with the microprocessor between 8086~80286, it is a 16-bit instruction, which means that the instruction is in the default mode a 16-bit offset address and a 16-bit register, which is often referred to as a 16-bit instruction mode. If d==1: Then the instruction is a 32-bit instruction, by default the 32-bit instruction description assumes that all Kad and registers are 32-bit. (Zc:kad?) What is it? "17:42" 8th to 16th bit (Zc:p/dpl/s/type): Is the access byte, which controls access to the memory segments in protected mode. This byte (ZC: Here refers to "access byte" or "S"?) Describes how a segment works in a system. Access permissions bytes are fully controlled in the segment. If the data segment specifies its direction of growth, if the segment grows beyond its bounds, the microprocessor's program is interrupted and a general protection error is given. The user can indicate whether a data segment is writable or write-protected. You can also control code snippets in a similar way.    To protect the software, you can also disable reading. The "18:45" descriptor is selected from the Descriptor table by the segment register. The segment register contains a 13-bit segment selector subfield. TI: Table selection field.        RPL: The Request Priority field.        "19:23" 3~15-bit (total 13-bit) selection subfield, you can select one from the 8,192 descriptors of the descriptor list.        "19:35" TI: Indicates the global descriptor (Ti = = 0) or local descriptor (Ti = = 1). "19:58" RPL: Request Priority field.            The access priority of the request memory segment, the highest level ==0x00, and the lowest ==0x11. "20:23" If request priority and access permissions are setis allowed to be accessed if it matches or is higher than the priority level. The "20:33" priority is used in multi-user environments. If the priority is violated, the system is usually just a priority violation error.    "20:45" "2, Program invisible Register" The memory system has a global descriptor table and local descriptor tables, in order to access and specify the address of these lists, the microprocessor contains some program invisible registers.    "21:08" program is not visible refers to a normal program can not be accessed by the system software access can be accessed by the operating system kernel (the register).    "21:22" when operating in protected mode, these registers (program invisible Registers) control the microprocessor. "21:35" GDTR: Global Descriptor Descriptor Register "21:38" IDTR: Interrupt Descriptor Tabulation Register "21:43" task register:tr tasks Register "21:47" LDTR: Local Descriptor Descriptor Register "21:55"        In protected mode, each segment register contains an invisible area of a program, and the program-invisible area of these registers is often referred to as a high-speed buffer/high-speed buffer (which translates to the cache, but the cache is not the same as the cache of level two caches in the microprocessor).        "22:25" when the number in the segment register changes, the base site boundary access permission is loaded into the program's invisible area of the segment register. "22:35" When a new segment number is placed in the segment register, the microprocessor accesses the descriptor list, and the program that loads the descriptor into the segment register is not visible in the high-speed buffer. This descriptor is always stored in this place, and is used when accessing memory segments until the segment number changes again.    This allows the microprocessor to repeatedly access the memory segment without having to query the descriptor descriptor every time, so it is called a cache register. "23:23" GDTR and IDTR contain the base site boundaries of the descriptor descriptor. The ∵ descriptor table has a maximum length of 64kb,∴ two tables with a limit of 16 bits.    "23:41" when working in protected mode, the global descriptor sheet base site bounds are loaded into the GDTR, and the middle descriptor idtr must be initialized before using protected mode. The location of the "24:08" Local Descriptor table is selected from the Global Descriptor list. In order to address the local descriptor list, a global descriptor is created, and when the local descriptor is accessed, the selector is loaded into the IDTR, as if the selector is loaded in the segment register. "24:39" This selects the global descriptor descriptor and accesses the base site boundary of the local descriptor descriptor.The permissions are loaded into the LDTR buffer memory. (ZC: Here, the "cache register" is changed to "buffer memory", whether the above is also wrong?) The "25:01" TR contains a selector that is used to access a defined task descriptor, which is usually a process/application. The process/application descriptor is stored in the Global descriptor table, so it can be accessed through priority control. The "25:33" task switching mechanism allows the microprocessor to switch between tasks in short enough time, and also allows a multitasking system to switch from one task to another in a simple and regular manner. "25:55" "paging mechanism 1, paging register" "26:03" 80386 and more advanced microprocessors its paging mechanism allows the address of the physical memory to be allocated for any linear address.    Linear address is the address generated by the program, through the memory paging mechanism linear address transparent conversion to physical address, so that the need to run at a specific address of the program through the paging mechanism to relocate.    "26:45" The contents of the control register in the microprocessor control the unit of paging, and the registers that are vital for paging units are CR0 and CR3. "27:02" CR0 the leftmost 31st digit PG bit: Set ==> Select the paging mechanism; PG 0 ==> The linear address generated by the program is the physical address located in the addressable memory.    When the PG is 1, the linear address is converted to a physical address by the paging mechanism. "27:35" CR3 content, including the page directory base site and the PCD and PWT. We mainly explain the page directory base address, which is from 12th to 31st bits.        The page directory base address is a page directory that is addressed by the page conversion assembly, which addresses a page directory with 4 K boundaries in memory.        ZC: "Page directory base address for page conversion parts Addressing page directory", see "Intel Micro-processing architecture. docx". The "28:16" page directory contains 1024 (page) catalog entries, each with a length of 4 bytes.    Each page catalog entry addresses a page table that contains 1024 items. "28:38" is a linear address generated by the software, divided into 3 parts, respectively, for addressing page directory entries (directory), page table entries (table), offset addresses (offset). Each page directory entry represents a region of 4M for the storage system, and the contents of the page catalog are selected by the subsequent 10-bit linear address indicated by the page table, which is a 4K area. The offset portion of the linear address selects one byte in the 4K page. ∵ to re-paging the 4K store requires access to the page Directory and page table in memory, ∴intel creates a highBuffer memory. If you want to access a store and its address is already in the TLB, then you do not need to access the page directory and page table, thus speeding up the execution of the program. If a page table conversion is not in the TLB, you must access the page directory and the page table. "30:13" "2, page catalog and page table" "30:25" figure shows how to convert a linear address into a physical address of a process. It (ZC: linear address?) 22nd to 31st bit, specifying the page directory, the base address of the page directory is determined by CR3, it (ZC:CR3 PDBR?        ) specifies a directory entry in the page directory.        "30:50", 12th through 21st, specifies a page table entry in one of the catalog entries. "31:00" offset, then the offset value plus the page table entry constitutes the physical address.    "31:15" "Storage Management unit in 80386 Storage management 1, descriptors and selectors" 31:23 "80386 the MMU and the MMU in 286 are very similar, except that 80386 contains no paging unit 286.    The "31:41" MMU is used to convert the linear address of the output in the program into a physical address. "31:51" 80386 uses a paging mechanism to assign a physical address to a logical address, so if paging is active even if the program instruction requires access, such as the actual physical address of the A0000 unit may be a 10000H unit or other unit.    This feature actually enables the software that operates on any storage unit to run on 80386, ∵ any linear address can be transformed into a physical address. The "32:38" descriptor is a 8 contiguous byte that describes and locates the memory segment.    The select child is used to retrieve the descriptor from the descriptor table.    The descriptor for "32:52" 80386 uses the 32-bit base address and 20-bit bounds.    "33:01" 80386 uses a 32-bit base address to address 4G of storage space. "33:10" because it has 20-bit boundaries in two different ways, its length can be 1M or 4G.    Why the 1M and 4G, is the reason for the ∵ particle size g-bit, G-bit 0 o'clock is the 1m,g bit is 1 when the maximum length of the allowed address is 4G. "33:45" This figure (ZC: The above chart) illustrates how 80386 in protected Mode, the selection sub-descriptor, descriptors to address the memory segment. Select the child with its leftmost 13 bits select a descriptor from the description schedule, TI bit (ZC: Is there a wrong answer?). Indicates whether the local descriptor table or global descriptor tables are indicated.        We mentioned that Ti==0 is a global descriptor table, and Ti==1 is a local descriptor. "34:28"Select the two-bit RPL at the far right of the child, as we have also said, to define the required access priority levels.    The "34:40" selector selects a descriptor in the descriptor table with the base address of the segment, which gets the linear address we want by removing the base site plus the offset address. "34:58" because the selector is a 13-bit code access descriptor, it's the entire 16-bit (zc:13+2=15, what else does one do?) ), the ∴ can have up to 8,192 descriptors in each local/global descriptor table. Since each segment can be 4G, and we can access 16,384 segments with two descriptor, this allows 80386 virtual memory addresses that can be accessed to reach 64t,1t=1024g. "36:18" Memory system actually exists memory is 32-bit address line, ∴ can only be 4G.    If, at some point, a program needs more than 4G of memory, it can swap memory systems with disk drives or other forms of mass storage devices. "36:45" 80386 has a global descriptor and a local descriptor, and an interrupt descriptor, IDT.    IDT is designed for interrupt descriptors or door descriptors. The base address for "37:11" 80386 is a 32-bit boundary field that is 20 bits.    The G-bit indicates the particle size, which can be either 1 or 4K in multiples.        "37:35" Let's take a look at the descriptor (ZC: the picture below) and see what each bit means. "37:50" the No. 0 to 15th digit indicates the segment limit length.        The length of the segment is also 16th to 19th, and the combination of the two is the actual length of the segment limit. "38:08" 16th to 31st bit is the base address. 5th byte It is also the base address, so 5th, 4, 3 bytes also have 16th bit to 31st bit (ZC: should actually be 56th bit to 63rd bit?).        Their combination makes up the value of the base address.        ZC: Here you can see that the descriptor is 64 bits long.        "38:45" d/b bit: It is used to select the width of the default register, if the width of the d==0 register is 16 bits, if the width of the d==1 register is 32 bits. "39:09" AVL: is used by the operating system in an appropriate manner, and is typically used to indicate whether the segment described by the descriptor is available. "39:27" "2, Segment Descriptor 3, System descriptor" "39:38" ZC: This picture is a segment descriptor?    Not a system descriptor? The access permission bit for the "39:45" segment is these (ZC: The 8-16/40-48 bit in the video that seems to be the middle finger, p/Dpl/s/type).        The access permission bit is used to indicate how the data segment, stack segment, or code snippet described by the descriptor is working. The 4th byte of the "40:12" access permission is S (ZC: The description above does refer to P/dpl/s/type), which indicates that the descriptor is a system descriptor/data Descriptor/code descriptor.        S==0, which represents a system descriptor, s==1, is a normal descriptor (possibly a data descriptor or code snippet descriptor) ZC: Here the sense that the structure of the segment descriptor and system descriptor should be the same, all of which are structures within the diagram. "40:47" P: There is a bit.        P==1 indicates that the segment is present, p==0 and accessing the segment via a descriptor generates a Type 11 interrupt that indicates that the segment accessed does not exist in the system. "41:17" DPL: Describes descriptor precedence, which is used to set the precedence of descriptors. 00 represents the highest priority, and 11 represents the lowest priority. Used to protect access to a segment. If you use a lower priority than DPL to access this segment, an ultra vires outage occurs.        The priority in a multiuser system prevents access to the system store "42:06" S==0 represents a system segment, and S==1 represents a data segment or code snippet. "42:24" Type occupies 4 bits, 4 bits have several flags, from high to low to the e mark, x mark, RW flag, a flag "42:58" e-bit: executable bit.            Used to select data/code Snippets.                "43:07" x-bit: When e-bit ==0, X indicates the expansion direction of the data segment/stack segment--and X==0, the segment expands upward like a data segment, and if X==1, the segment expands downward like a stack segment.            When E==1, x indicates that the code snippet's priority is ignored. "43:38" RW bit: If the E==0,RW bit indicates whether the data segment is allowed to write. If the E==1,RW bit indicates whether the code snippet is allowed to read.            Allow is 1, not allowed is 0. "44:03" a bit: Access bit. Each time the processor accesses a segment, the bit is set to 1.    The operating system uses this bit to track those segments that have been accessed.    "44:20" look again. System descriptor "44:28" System descriptor s bit 0 o'clock, descriptor is System descriptor. "44:33" 80386 there are 16 possible system descriptor types in the system, but not all are used in 80386, and some types are for80286 is defined so that the software on 80286 is compatible with 80386.        Some types are newly defined and are 80386 unique, others are not defined and are reserved for subsequent products.        ZC: Are these types defined by the hardware manufacturer?? What does "45:10" say about the 16 possible descriptor types, each of which type is based on the Type,∵type is 4 bits, using the type to distinguish what kind of system descriptor it is.            See for yourself: type==0, invalid.            Type==1, used for 286 of the task status segment.            type==2, used for the LDT to represent local descriptors.            A type==3 that indicates that the descriptor is performing 80286 of the task State segment.            Type==4, which represents the 80286 call gate.            TYPE==5, Mission Gate.            type==6,80286 of the broken door.            Type==7,80286 's trap door.            Type==8, invalid.            Type==9,80386 the task status segment.            type==10, reserved for future Intel products.            TYPE==11, the 80386 task status segment that is being executed.            Type==12,80386 the calling door.            Type==13, reserved for future Intel products.            Type==14,80386 of the broken door. Type==15,80386 's trap door. Finished

1, Eflags_01.jpg

2, Eflags_02.jpg

3, Eflags_03.png

4, Segment Descriptor _01.jpg

5, Segment Descriptor _02.jpg

6, Segment selector (or segment selector) _01.jpg

7, Segment selector (or segment selector) _02.gif

8, program invisible Register. jpg

9, paging register. jpg

10. Page catalog and page table. jpg

11, descriptors and selectors. jpg

12, paragraph descriptor? System descriptor?. jpg

C

Two--(1)