TXB0108 txs0108e 8-bit bidirectional voltage-level Translator for Open-drain and push-pull applications

TXS (open-drain optimized design) such as I²c

TXB (pull-up optimized design), such as SPI

TXS0108 have integrated pull-up resistors to save board space and cost in open-drain applications.

The TXS0108 Does not need external pullup resistors.

The TXS0108 is intended for high drain devices and external pullups would cause problems.

Integrating the pullups into the chip is the main differerance between the TXS0108 and TXB0108.

For the sake of search ability, this is the same for the TXS0102, TXS0104, TXS0106.

To address the application requirements for both Push-pull and Open-drain mode,

A semi-buffered architecture design is used and was illustrated below (see Figure 5).

Edge-rate Accelerator circuitry (for both the high-to-low and low-to-high edges),

A High-ron n-channel pass-gate transistor (on the order of 300ωto 500ω)

and pull-up resistors (to provide dc-bias and drive capabilities) is included to realize this solution.

A Direction-control signal (to control, the direction of data flow from a to B, or from B to a) are not needed.

The resulting implementation supports both Low-speed Open-drain operation as well as high-speed push-pull operation.

When the transmitting data from A-to B-ports,

During a rising edge the one-shot (OS3) turns on the PMOS transistor (P2) for a short-duration

And this speeds the low-to-high transition.

Similarly, during a falling edge, when transmitting data from a to B, the one-shot (OS4) turns on NMOS transistor (N2) for A short-duration

And this speeds the high-to-low transition.

The B-port edge-rate Accelerator consists of One-shots OS3 and OS4,

Transistors P2 and N2 and serves to rapidly force the B port high or low when a corresponding transition are detected on th e A Port.

When the transmitting data from B-to A-ports,

During a rising edge the one-shot (OS1) turns on the PMOS transistor (P1) for a short-duration

And this speeds the low-to-high transition.

Similarly, during a falling edge, when transmitting data from B to A, the one-shot (OS2) turns on NMOS transistor (N1) for A short-duration

And this speeds the high-to-low transition.

The A-port edge-rate Accelerator consists of One-shots OS1 and OS2,

Transistors P1 and N1 components and form the Edge-rate accelerator and serves to rapidly force the A, Port high, or low

When a corresponding transition was detected on the B port.

TXB0108 txs0108e 8-bit bidirectional voltage-level Translator for Open-drain and push-pull applications