U-boot for smart210 (rookie from zero-learning LINUX) __linux

Just started to learn Linux, today to transplant u-boot on the friendly smart210 board. Official website to obtain opencsbc-u-boot-mini210_linaro-2011.10-stable.tar.gz,mini210 u-boot. (Instructor: Splashing splashing LK)

1, enter the command under mini210 extract the current file:

$make Arch=arm Cross_compile=/opt/friendlyarm/toolschain/4.5.1/bin/arm-none-linux-gnueabi-tiny210_config

The sentence command is used to pass parameters to the total makefile. Arch=arm incoming parameters are configured to run the board level CPU, Cross_compile is the path to the cross tool chain corresponding to its board level. If you have set the environment variable, you can add it directly to the makefile cross_compile=arm-none-linux-gnueabi-

Tiny210_config is the assignment of the corresponding parameter to the BOARDS.CFG and then executes the mkconfig. Define two steps as Tiny210_config. After the above settings, subsequent debugging can be directly entered make tiny210_config.

2, compile the mini210_uboot, make all SPL. The corresponding first stage bin file Mini210-spl.bin into the first sector of the SD card, the second phase of the bin file U-boot.bin file into the 49th sector. Why the second phase is copied to 49 sectors, because the first phase of U-boot code is moved to Iram by Irom's fixed-line code. Only 24K to Iram were moved according to the manual. Each sector is 512 bytes, then the first 48 sectors is just 24K, the second stage is after 24K, of course, this second phase of the sector can also be changed, need to move the code in the second phase changes can be. The commands for copying into sectors are:

$sudo DD iflag=dsync oflag=dsync if=spl/tiny210-spl.bin of=/dev/sdb seek=1
$sudo DD iflag=dsync oflag=dsync if=u-boot.bin of=/dev/sdb seek=49

3, the board on the electric SD card operation can see the display OK, so that this mini210 u-boot on the smart210 on the failed to run up. We need to set up LED lights to see where they might go wrong. Used in start. Set the LEDs in S to see where the error may be initialized. Found that LED lights can be lit no problem, then the possible place may be moved part of the initialization of memory or move. We are in the second phase of the Board_init_r set another lamp to see what it shows. proved to be a problem with memory initialization.

4, we start to see if mini210 's memory initialization matches its own smart210 memory. The core code for memory initialization is/board/samsug/mini210/memsteup. S This code does not have code errors for ARMV7 with the same architecture as the core. It may only appear on the memory control registers, the mini210 memory configuration from the/include/configs/mini210.h. are modified in.

/* Memtest works on * *

#define CONFIG_SYS_MEMTEST_START memory_base_address * * Memory initial address no need to modify * *

#define Config_sys_memtest_end (memory_base_address + 0x3e00000)/MB in DRAM, which is not modified here, is to be determined, defined here in Get_ram_size ((long *) phys_sdram_1, phys_sdram_1_size);

function is not used, is some old version of the legacy of only detection of 64M, while the new detection 512m*/

#define CONFIG_SYS_LOAD_ADDR (phys_sdram_2 + 0x0100 0000)//default load address defaults to download, you can change the first bank area without modification. Here if it is bank2 from 0x3000 0000+0x0100 0000 is 0x3100 0000 out of the beginning, Bank1 is starting from 0x2100 0000, used in commands such as serial transmission commands.

/* MINI210 has 4 Bank of DRAM * *

#define CONFIG_NR_DRAM_BANKS 2/* divided into 2 parts * *

#define SDRAM_BANK_SIZE 0x10000000/* 256256 MB * *

#define PHYS_SDRAM_1 memory_base_address/* Start address of the first part * *

#define Phys_sdram_1_size Sdram_bank_size

#define PHYS_SDRAM_2 (memory_base_address + 0x20000000)/* SDRAM Bank #2 This is the second part of the starting address, because we only used a DRAM0 so the address should be changed to Memory_base _address + 0x10000000 512M is divided into 2 parts * *

#define Phys_sdram_2_size Sdram_bank_size

The address map is as follows:

Modify the corresponding control register (red pen display at the change):

#if defined (config_mcp_single)

#define Dmc0_memcontrol 0x00202400//Memcontrol bl=4, 1Chip, DDR2 Type, dynamic Self refresh, Force precharge, Dynamic PO Wer down

#define DMC0_MEMCONFIG_0 0x20e00323//MemConfig0 256MB config, 8 banks,mapping method[12:15]0:linear, 1:linterleaved, 2: Mixed

#define DMC0_MEMCONFIG_1 0x00e00323//MEMCONFIG1

#if 0

#define DMC0_TIMINGA_REF 0x00000618//Timingaref 7.8us*133mhz=1038 (0x40e), 100mhz=780 (0x30c), 20mhz=156 (0x9C), 10MHz= (0x4e)

#define Dmc0_timing_row 0x28233287//Timingrow for @200mhz

#define DMC0_TIMING_DATA 0x23240304//Timingdata cl=3

#define DMC0_TIMING_PWR 0x09c80232//Timingpower

#else

#define DMC0_TIMINGA_REF 0x00000618//Timingaref 7.8us*133mhz=1038 (0x40e), 100mhz=780 (0x30c), 20mhz=156 (0x9 C), 10mhz=78 (0x4e)

#define Dmc0_timing_row 0x2b34438a//Timingrow for @200mhz

#define DMC0_TIMING_DATA 0x24240000//Timingdata cl=3

#define DMC0_TIMING_PWR 0x0bdc0343//Timingpower

#endif

S5PV210 has two separate DRAM controllers, DMC0 and DMC1, DMC0 maximum support 512MBYTE,DMC1 1GByte, while DMC0 and DMC1 also support two slices CS0 and CS1. Revise the similarities and differences according to the data manual.

CHIP_MASK[23:16]

These 8 bits are used to determine the offset of the chip0 in the memory address, that is, to set the DRAM capacity that the chip0 is connected to. For example, if you set CHIP_MASK=0XE0. Replace it with binary as: 0b1110_0000, then it will shield the highest three bits [31:29], then the result is: 0b0001_1111, that is 0x1f. The rest of the lower 24 bits are padded with 1, then the capacity of the DRAM on the DCM0 chip0 is 0x1fff_ffff. The range of addresses to get Chip0 is: 0x2000_0000~0x3fff_ffff. That is, the capacity is 512MByte.

CHIP_MAP[15:12]

The 8-bit function is to determine the address mapping method of DRAM.

Chip_col [11:8]

The number of bits to set the address of the column.

Chip_row[7:4]

The number of bits to set the row address.

CHIP_BANK[3:0]

The number of logical bank.

Next, migrate the TCPIP.