U-boot porting (2)

(4) Disable the watchdog.

Ldr r0, = pWTCON

Mov r1, #0x0

Str r1, [r0]/* When the detection bit of the watchdog controller is 0, the watchdog does not output a reset signal */

The above code writes 0 to the watchdog control register and disables the watchdog. Otherwise, the CPU will be continuously restarted during U-Boot.

(5) Block interruption

/*

* Mask all IRQs by setting all bits in the INTMR-default

*/

Mov r1, #0 xffffffff/* the interrupt corresponding to a set of 1 is blocked */

Ldr r0, = INTMSK

Str r1, [r0]

INTMSK is the main interrupt shielding register. Each bit corresponds to one of the SRCPND (interrupt source pin register), indicating whether the interrupt request is processed by the CPU.

According to reference 4, The INTMSK register is a 32-bit register. Each register corresponds to an interrupt. Write 0xffffffff to it, and all the positions of the INTMSK register are one, thus shielding the corresponding interrupt.

# If defined (CONFIG_S3C2440)

Ldr r1, = 0x7fff

Ldr r0, = INTSUBMSK

Str r1, [r0]

# Endif

Each bit of INTSUBMSK corresponds to one of the SUBSRCPND, indicating whether the interrupt request of the SUBSRCPND is processed by the CPU.

According to reference 4, The INTSUBMSK register is a 32-bit register, but only uses 15 lower bits. Writing 0x7fff to it sets all the valid bits (15 low bits) of the INTSUBMSK register to one, thus shielding the corresponding interruption.

(6) Set MPLLCON, UPLLCON, CLKDIVN

# If defined (CONFIG_S3C2440)

# Define MPLLCON 0x4C000004

# Define UPLLCON 0x4C000008

Ldr r0, = CLKDIVN

Mov r1, #5

Str r1, [r0]

 

Ldr r0, = MPLLCON

Ldr r1, = 0x7F021

Str r1, [r0]

 

Ldr r0, = UPLLCON

Ldr r1, = 0x38022

Str r1, [r0]

# Else

/* FCLK: HCLK: PCLK = */

/* Default FCLK is 120 MHz! */

Ldr r0, = CLKDIVN

Mov r1, #3

Str r1, [r0]

# Endif

After several milliseconds of CPU power-on, the crystal oscillator output is stable. FCLK = Fin (crystal oscillator frequency), and the CPU starts to execute commands. But in fact, FCLK can be higher than Fin. To improve the system clock, you need to use software to enable the PLL. In this case, you need to set the three registers CLKDIVN, MPLLCON, and UPLLCON.

The CLKDIVN register is used to set the ratio between FCLK, HCLK, and PCLK. It can be set according to Table 2.2.

Table 2.2 CLKDIVN register format of S3C2440

CLKDIVN	Bit	Description	Initial Value
HDIVN	[2:1]	00: HCLK = FCLK/1. 01: HCLK = FCLK/2. 10: HCLK = FCLK/4 (when CAMDIVN [9] = 0) HCLK = FCLK/8 (when CAMDIVN [9] = 1) 11: HCLK = FCLK/3 (when CAMDIVN [8] = 0) HCLK = FCLK/6 (when CAMDIVN [8] = 1)	00
PDIVN	[0]	0: PCLK = HCLK/1 1: PCLK = HCLK/2	0

 

If CLKDIVN is set to 5, HDIVN is set to 10 of binary. Because CAMDIVN [9] has not been changed, the default value is 0, so HCLK = FCLK/4. PDIVN is set to 1, so PCLK = HCLK/2. Therefore, the FCLK: HCLK: PCLK =.

The MPLLCON register is used to set the multiples of FCLK and Fin. The position [] of MPLLCON is called MDIV, and the position [] is called PDIV, and the position [1:0] is called SDIV.

For the relationship between S3C2440, FCLK and Fin, see the following formula:

MPLL (FCLK) = (2 × m × Fin)/(p × 142s '>)

Where: m = MDIC + 8, p = PDIV + 2, s = SDIV

The values of MPLLCON and UPLLCON can be set based on the "pll value selection table" in reference 4. The table is excerpted as follows:

Table 2.3 Recommended PLL values

Input frequency	Output Frequency	MDIV	PDIV	SDIV
12.0000 MHz	48.00 MHz	56 (0x38)	2	2
12.0000 MHz	405.00 MHz	127 (0x7f)	2	1

When the clock speed of the mini2440 system is set to 405 MHZ and the USB clock frequency is set to 48 MHZ, the system can run stably. Therefore, MPLLCON and UPLLCON are set:

MPLLCON = (0x7f <12) | (0x02 <4) | (0x01) = 0x7f021

UPLLCON = (0x38 <12) | (0x02 <4) | (0x02) = 0x38022