UART, SPI, and i²c explanations

To do SCM Development UART,SPI and I²c are our most commonly used hardware interface, I collected the relevant specific materials on these three kinds of interfaces are explained in detail.

Uart

The UART is a universal serial data bus that is used for asynchronous communication. The bus bidirectional communication, can achieve full duplex transmission and reception. In the embedded design, the UART is used for communication between the host and the auxiliary device, such as the communication between the car stereo and the external AP, and the PC communication includes the communication with the monitor debugger and other devices such as EEPROM.

Converts the parallel data transmitted from inside the computer to the output serial data stream. Converts the serial data from outside the computer to bytes for use by devices that have parallel data inside the computer. The parity bit is added to the output serial data stream, and the data stream received from the outside is parity. Add a start-stop flag to the output data stream and remove the start-stop flag from the receiving data stream. Handles interrupt signals that are issued by the keyboard or mouse (the keyboard and mouse are also serial devices). Can handle the problem of synchronization management between the computer and the external serial device. Some of the more upscale UART also provides buffers for input and output data, compared to the new UART is 16550, which can store 16 bytes of data in its buffer before the computer needs to process the data, while the usual UART is 8250.

Interface

In the microcontroller in the UART can be said to be a basic configuration, a lot of communication with the computer equipment used to it, according to the most conventional version of the computer is serial communication.

• TX-Data Send interface
• RX-Data Reception interface

The TX is connected to the RX between the two devices, and the RX is connected to TX for normal operation. The most common is the USB on our computer that is the most typical UART interface.

How it works send receive

The send logic performs a "and → string" Conversion of the data read from the Send FIFO. The control logic outputs a first-bit serial bit stream, and according to the programmed configuration in the control register, the data bits are followed (note: the lowest bit LSB outputs first), the parity bit, and the stop bit.
After a valid starting pulse is detected, the receiving logical docking receives the bit stream to perform a "string → and" conversion. Overflow errors, parity errors, frame errors, and line abort (line-break) errors are also detected, and the detected state is appended to the data that is written to the receive FIFO.

Baud Rate generation

The baud rate divisor (baud-rate divisor) is a 22-bit number that consists of 16-bit integers and 6-bit decimals. The baud rate generator uses a number consisting of these two values to determine the bit period. With a divider with a fractional baud rate, the UART can generate all standard baud rates at a sufficiently high system clock rate, with little error.

Data sending and receiving

When sent, the data is written to the send FIFO. If the UART is enabled, it will start sending data in accordance with pre-set parameters (baud rate, data bit, stop bit, check digit, etc.) until there is no data in the transmit FIFO. Once the data is written to the transmit FIFO (if the FIFO is not empty), the UART's busy flag bit busy is valid and remains valid for the duration of the data being sent. The BUSY bit only becomes invalid when the send FIFO is empty and the last character is sent from the shift register, including the stop bit. That is, the UART is no longer enabled, it can also indicate a busy state. BUSY-bit related library function is uartbusy ()
When the UART receiver is idle, if the data input becomes "low", i.e. the start bit is received, the receive counter starts running and the data is sampled in the 8th cycle of the BAUD16. If the RX is still low in the 8th cycle of the BAUD16, the start bit is valid, otherwise it is considered to be the wrong starting bit and is ignored.
If the starting bit is valid, the continuous data bits are sampled for each 16th cycle of the Baud16 (after a bit cycle), based on the length of the data character being programmed. If the parity mode is enabled, the parity bit is also detected.
Finally, if Rx is high, a valid stop bit is confirmed, otherwise a frame error occurs. When a full character is received, the data is stored in the receive FIFO.

Interrupt control

The UART can be interrupted when the following conditions occur:

• FIFO overflow Error
• Line Abort error (Line-break, i.e. the RX signal has been in the state of 0, including the check bit and stop bit)
• Parity errors
• Frame error (Stop bit is not 1)
• Receive timeout (receive FIFO data but not full, and subsequent data does not come for a long time)
• Send
• Receive

Because all interrupt events are "or operations" together before they are sent to the interrupt controller, the UART can only generate an interrupt request to the interrupt at any time. By querying the interrupt State function Uartintstatus (), the software can handle multiple interrupt events (multiple if statements) in the same interrupt service function.

FIFO operation

FIFO is the abbreviation for "first-in first-out", meaning "FIFO", which is a common queue operation. The UART module of the Stellaris series arm contains 2 16-byte FIFO: one for sending and the other for receiving. The two FIFO can be configured to trigger interrupts at different depths, respectively. Available configurations include: 1/8, 1/4, 1/2, 3/4, and 7/8 depth. For example, if you receive a FIFO selection of 1/4, a receive interrupt is generated when the UART receives 4 data.

send FIFO basic work process : As long as the data is populated into the send FIFO, the sending process starts immediately. Since the sending itself is a relatively slow process, other data that needs to be sent while it is being sent can continue to be populated into the send FIFO. When the send FIFO is filled, it can no longer be populated, otherwise it can cause data loss, which can only wait at this time. This wait will not be long, take 9600 baud rate as an example, waiting for the time to appear a vacancy in 1ms up and down. The send FIFO sends the data in the order in which it is filled in, until the FIFO is fully empty. The data that has been sent is automatically cleared and an extra space is available in the Send FIFO.

the basic process of receiving a FIFO : When the hardware logic receives the data, it fills in the received FIFO with the received data. The program should take this data in time, the data is removed in the receiving FIFO is automatically deleted process, so in the receiving FIFO at the same time there will be an extra empty. If the data in the receiving FIFO is not taken out in time and the receiving FIFO is full, then the data will be lost if no vacancy can be filled in the future.

Transceiver FIFO is mainly to solve the problem that the UART transmit and receive interrupts are too frequent and lead to low CPU efficiency. In the UART communication, the interrupt mode is simpler and more efficient than the polling method. However, if you do not send and receive FIFO, then each data sent and received to interrupt processing once, the efficiency is still not high enough. If you have a send and receive FIFO, you can send and receive several data (up to 14) to generate a single interrupt and then processed together, which greatly improves the transceiver efficiency.

There is absolutely no need to worry about the FIFO mechanism may be caused by the loss of data or can not be processed in a timely manner, because it has helped you think of any problems in the sending and receiving process, as long as the initial configuration of the UART, you can safely send and receive, FIFO and interrupt routines will automatically take care of everything.

Loopback operations

The UART can enter an internal loopback (Loopback) mode for diagnostic or debug purposes. In loopback mode, data sent from TX is received by the RX input.

Serial Infrared Protocol

In some Stellaris series ARM chips, the UART also contains an IrDA serial infrared (SIR) encoder/decoder module. The IrDA SIR module acts as a conversion between the asynchronous UART data stream and the half-duplex serial Sir interface. No simulated processing operation is performed on the chip. The task of the SIR module is to provide a digital encoded output and a decoding input to the UART. The UART signal pin can be connected to an infrared transceiver to enable the IrDA Sir Physical layer connection.

I2c

I²c Bus is a simple, bidirectional two-wire synchronous serial bus developed by Philips Corporation. It requires only two wires to transmit information between devices connected to the bus.
The main device is used to start the bus to transmit data and produce a clock to open the transmitting device, at which point any addressed device is considered to be from the device. The relationship between primary and outgoing on the bus is not constant, but depends on the direction of data transmission at this time. If the host is to send data to the slave device, the host first addresses the slave device, then proactively sends the data to the slave device, and finally terminates the data transmission by the host, if the host is to receive data from the device, the primary device is first addressed from the device. The host then receives the data sent from the device and finally terminates the receive process by the host. In this case. The host is responsible for generating timed clocks and terminating data transfers.

Interface

1. SCL-Serial clock line
2. SDA-Serial Data cable interface

SDA (serial data line) and SCL (serial clock line) are bidirectional I/O lines, and the interface circuit is an open-drain output. The power supply must be connected to VCC via a pull-up resistor. When the bus is idle. Two lines are high level, the external device connected to the bus is a CMOS device, the output stage is also open-drain circuit. The amount of current that is consumed on the bus is very small, so the number of devices extended on the bus is largely determined by the capacitive load, because the bus interface of each device has a certain equivalent capacitance. The capacitance in the circuit will affect the bus transmission speed. When the capacitance is too large, it is possible to cause transmission errors. Therefore, its load capacity is 400pF, so it can estimate the bus allowable length and the number of devices to be connected.

The main device is used to start the bus to transmit data and produce a clock to open the transmitting device, at which point any addressed device is considered to be from the device. The relationship between primary and outgoing on the bus is not constant, but depends on the direction of data transmission at this time. If the host is to send data to the slave device, the host first addresses the slave device, then proactively sends the data to the slave device, and finally terminates the data transmission by the host, if the host is to receive data from the device, the primary device is first addressed from the device. The host then receives the data sent from the device and finally terminates the receive process by the host. In this case. The host is responsible for generating timed clocks and terminating data transfers.

Characteristics

The features of the I²C bus can be summarized as follows:

• On the hardware, the I²C bus only needs a data cable and a clock line two lines, the bus interface has been integrated in the chip, no special interface circuit is required, and the filter on the on-chip interface circuit can filter out the Burr on the bus data. Therefore, the I²C bus simplifies the PCB wiring of hardware circuit, reduces the system cost and improves the system reliability. Because the I²C chip in addition to these two lines and a small number of wire break, and the system is no longer connected to the line, the user commonly used IC can easily form a standardized and modular, easy to re-use.
• I²c Bus is a true multi-host bus, if two or more hosts simultaneously initialize the data transmission, can be prevented by conflict detection and arbitration to prevent the destruction of information, each device connected to the bus has a unique address, any device can be either as a host or as a slave, but only one host is allowed at the same time. Data transfer and address settings are set by the software and are very flexible. Device additions and deletions on the bus do not affect the normal operation of other devices.
• I²c bus can be detected by external connection, easy to diagnose and debug the system, fault can be addressed immediately, software is also conducive to standardization and modularization, shorten the development of the question.
• The number of ICS connected to the same bus is limited only by the maximum capacitance of the bus, the serial 8-bit bidirectional data transfer bit rate in standard mode up to 100kbit/s, fast mode up to 400kbit/s, high-speed mode up to 3. 4mbit/s.
• The bus has very low current consumption. High noise immunity, increased bus driver can increase the bus capacitance 10 times times, transmission distance of 15m, compatible with different voltage levels of the device, the operating temperature range is wide.

Data transfer Mode byte format

Each byte sent to the SDA line must be 8 bits, and the number of bytes that can be sent per transmission is unrestricted. Each byte must be followed by a response bit. The first transmission is the highest bit (MSB) of the data, if from the confidential completion of some other functions (such as an internal Interrupt service program) to receive or send the next full data byte, you can keep the clock line SCL low, forcing the host to enter the waiting state, The data transfer continues when the slave is ready to receive the next data byte and releases the clock line SCL.

Answer response

The data transmission must be responsive, and the associated response clock pulses are generated by the host. During the clock pulse of the response the transmitter releases the SDA line (high).

During the response clock pulse, the receiver must pull the SDA line low so that it remains stable at low levels during the high level of the clock pulse.
Normally addressed receivers, after each byte received, must produce a response in addition to the data that begins with the Cbus address. When the slave cannot respond to the slave address (for example, it is performing some real-time functions that cannot be received or sent), the slave must keep the data line high, and the host then generates a stop condition to terminate the transmission or to produce a repeating starting condition to start a new transmission.

If the slave receiver responds to the slave address but cannot receive more data bytes after a period of transmission, the host must terminate the transmission again. This condition is represented by a slave that does not produce a response after the first word. The slave keeps the data line high, and the host produces a stop or repeat start condition.

If there is a host sink in the transport, it must generate a response from the last byte emitted by the slave, notifying the slave sender of the end of the data. The slave transmitter must release the data cable, allowing the host to produce a stop or repeat start condition.

Clock synchronization

All hosts generate their own clocks on the SCL line to transmit messages on the I²C bus. The data is valid only at the high cycle of the clock, so a deterministic clock is required for bit-wise quorum.

Clock synchronization is performed through the line with the Connect I²c interface to the SCL line. This means that the high to low switching of the SCL line causes the device to start counting their low-level cycles, and once the device's clock becomes low, it keeps the SCL line in this state until it reaches the high clock level. However, if the other clock is still low-level, the low-to-high switching of the clock does not change the status of the SCL line. Therefore, the SCL line is kept low by the device with the longest low-level cycle. At this point, low-cycle devices will enter a high-level waiting state.

When all the relevant devices have counted their low-level cycles, the clock line is released and turned high. Then the state of the device clock and the SCL line are not different, and all devices start counting their high-level cycles. The device that completes the high-level cycle first pulls the SCL line down again.

The low-level period of the resulting synchronous SCL clock is determined by the device with the longest clock cycle, while the high-level period is determined by the device with the shortest period of the clock.

Transfer Mode quick mode

Fast mode devices can be received and sent under 400KBIT/S. The minimum requirement is that they can be synchronized with the 400kbit/s transmission, which extends the low-level period of the SCL signal to slow down the transmission. Fast mode devices are backwards compatible and can communicate with standard mode devices in the 0~100KBIT/S I²c bus system. However, because standard mode devices are not up-to-the-line compatible, they cannot work in a fast-mode I²c bus system. The fast Mode I²C bus specification has the following characteristics compared to the standard mode:

1. The maximum bit rate is increased to 400kbit/s;
2. Adjusted timing of serial data (SDA) and serial clock (SCL) signals;
3. The input of the fast mode device has the function of suppressing burrs, and the SDA and SCL input have Schmitt trigger;
4. The output buffer of the fast mode device has a slope control function on the falling edge of SDA and SCL signal;
5. If the power supply voltage of the fast mode device is turned off, the I/O pins of SDA and SCL must be suspended and the bus cannot be blocked;
6. External pull-up devices connected to the bus must be adjusted to accommodate a shorter maximum allowable rise time for the fast mode I²c bus. For buses with a maximum load of 200pF, the pull-up device for each bus can be a resistor, and for a bus that loads between 200pf~400pf, the pull-up device can be a current source (max 3mA) or a switching resistor circuit.

High Speed mode

High-speed mode (Hs mode) devices have a huge breakthrough in the transmission speed of the I²C bus. Hs mode devices can transmit information at bit rates up to 3.4mbit/s and remain fully backwards compatible with fast mode or Standard mode (F/S mode) devices, which can communicate in two directions in a speed-mixed bus system.
Hs mode transmission has the same serial bus protocol and data format as the F/S mode system, in addition to not performing quorum and clock synchronization.

The high-speed mode I²C bus specification is as follows:

1. The Hs mode host device has an open-drain output buffer for the Sdah signal and an open-drain pull-down and current-source pull-up circuit at the SCLH output. This current source circuit shortens the rise time of the SCLH signal, and at any time in HS mode, only one host current source is active;
2. In the HS mode of multi-host systems, quorum and clock synchronization are not performed to speed up bit processing capability. The arbitration process usually ends with the F/S mode before transmitting the host code;
3. The Hs mode host device generates a serial clock signal at a ratio of high and low levels of 1:2. The timing requirements for establishing and maintaining time are lifted;
4. The HS mode device can be selected with a built-in bridge. In HS mode transmission, the HS mode device's high-speed data (Sdah) and high-speed serial clock (SCLH) lines are separated from the SDA and SCL lines of the F/S mode device through this bridge. Reduces the capacitive load on the Sdah and SCLH lines, making the rise and fall times faster;
5. The only difference in Hs mode from machine parts to f/s from machine parts is the speed at which they work. The Hs mode slave outputs a buffer with an open-drain output in the SCLH and Sdah. The SCLH pin-selectable drop-down transistor can be used to lengthen the low level of the SCLH signal, but only after the response bit is transmitted in the HS mode;
6. The output of the Hs mode device can suppress burrs, and the Sdah and SCLH outputs have a Schmitt trigger;
7. The output buffers of the Hs mode devices have a slope control function on the falling edge of the Sdah and SCLH signals.

Spi

The full name of the SPI interface is "Serial peripheral Interface", meaning the serial Peripheral interface, which Motorola first defined on its MC68HCXX series processor. The SPI interface is used primarily in EEPROM, FLASH, real-time clocks, ad converters, as well as between digital signal processors and digital signal decoders.

The SPI interface is a synchronous serial data transfer between the CPU and the peripheral low-speed device, in the shift pulse of the main device, the data is transmitted in bits, high in front, low in the rear, full-duplex communication, the data transmission speed is generally faster than the I²C bus, the speed can reach a few Mbps.

Interface

1. mosi– Master device data output, from device data input
2. miso– Master device data input, from device data output
3. sclk– clock signal, generated by the main device, up to FPCLK/2, from the maximum mode frequency of FCPU/2
4. nss– from the device enable signal, controlled by the main device, and some ICS are labeled CS (Chip Select)

In point-to-point communication, the SPI interface does not require addressing, and it is simple and efficient for full-duplex communication. in multiple slave device systems, each slave device requires a separate enable signal, which is slightly more complex than the I²C system on the hardware.

The SPI interface in the internal hardware is actually two simple shift registers, the transmitted data is 8 bits, the main device generated from the device enable signal and the shift pulse, the bitwise transmission, high position in front, low post.

Advantages and Disadvantages

• The protocol is simple and the relative data rate is high.
• More pins are occupied
• There is no flow control specified, and there is no response mechanism to confirm receipt of the data.

UART, SPI, and i²c explanations