Uboot DDR2 memory porting modification notes

Address: http://blog.csdn.net/lightsoure/archive/2010/09/22/5900500.aspx

Environment: s5pc100 + Android (uboot 1.3.4)

DDR2 256 MB

Due to the low power consumption advantage of DDR2 compared with mobile DDR and the high power consumption requirement of the product itself, it is necessary to use dd2 instead of mobile DDR;

Uboot linked list u-boot.LDS from/board/Samsung/smdkc100

 

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1. . Text:
2. {
3. CPU/s5pc1xx/start. O (. Text)
4. CPU/s5pc1xx/s5pc100/cpu_init.o (. Text)
5. Board/Samsung/smdkc100/lowlevel_init.o (. Text)
6. CPU/s5pc1xx/onenand_cp.o (. Text)
7. CPU/s5pc1xx/nand_cp.o (. Text)
8. CPU/s5pc1xx/movi. O (. Text)
9. * (. Text)
10. }

 

The entire uboot workflow is clear. We need to modify the memory configuration;

From start. s

/*
* Go setup memory and board specific bits prior to relocation.
*/

LDR sp, = 0xd0036000/* end of SRAM dedicated to U-boot */
Sub sp, SP, #12/* Set stack */
MoV FP, #0
 
 BL lowlevel_init/* Go setup PLL, MUX, memory */

And lowlevel_init. s

/* When we already run in Ram, we don't need to relocate U-boot.
* And actually, memory controller must be configured before u-boot
* Is running in Ram.
*/
LDR r0, = 0xff000fff
Bic R1, PC, R0/* R0 <-current base ADDR of code */
LDR R2, _ text_base/* R1 <-original base ADDR in Ram */
Bic R2, R2, R0/* R0 <-current base ADDR of code */
CMP R1, R2/* compare r0, R1 */
Beq 1f/* R0 = R1 then skip SDRAM init */

/* Init system clock */
BL system_clock_init
 
 BL mem_ctrl_asm_init knows that the memory-related configuration is in cpu_init.s. Okay, no worries. Directly paste the Configuration:

 

Step 1:

 

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1. /************ DLL initialization *************/
3. // LDR R1, = 0x6a101000 @ phycontrol0 DLL parameter setting
4. LDR R1, = 0x50101008 // added by S
5. STR R1, [r0, # dmc_phycontrol0]
8. // LDR R1, = 0x000000f4 // added by S
9. LDR R1, = 0x000000f6 // added by s the last bit is 6 for ddr21
11. STR R1, [r0, # dmc_phycontrol1]
13. // LDR R1, = 0x00000000 @ phycontrol2 DLL parameter setting
14. LDR R1, = 0x00000000 // added by S
15. STR R1, [r0, # dmc_phycontrol2]
17. // LDR R1, = 0x6a101002 @ DLL on
18. LDR R1, = 0x5010100a // added by S
20. STR R1, [r0, # dmc_phycontrol0]
22. // LDR R1, = 0x6a101003 @ DLL start
23. LDR R1, = 0x5010100b // added by S
25. STR R1, [r0, # dmc_phycontrol0]
29. LDR R2, = 0xe6000040 @ dmc_phystatus0
31. Loop1:
33. LDR R1, [R2] @ check DLL lock
34. ANDS R1, R1, #4
35. Beq loop1
37. LDR R1, [R2]
38. MoV R1, R1, LSR # (0x6)
39. And R1, R1, # (0xff)
40. MoV R1, R1, LSL # (0x18)
41. LDR R2, = 0xe6000018 @ dmc_phycontrol0
42. LDR R3, [R2]
43. Bic R3, R3, # (0xff000000)
44. ORR R1, R3, r2
45. STR R1, [R2]
49. // LDR R1, = 0x6a101003 @ force value locking
50. LDR R1, = 0x5010100b // added by S
51. STR R1, [r0, # dmc_phycontrol0]
53. // LDR R1, = 0x6a101009 @ DLL off
54. LDR R1, = 0x50101009 // added by S
55. STR R1, [r0, # dmc_phycontrol0]
56.  
57.  
58.  
59. # If 0
60. LDR R1, = 0x6a101000 @ phycontrol0 DLL parameter setting
61. STR R1, [r0, # dmc_phycontrol0]
63. LDR R1, = 0x00008484 @ phycontrol1 DLL parameter setting
64. STR R1, [r0, # dmc_phycontrol1]
66. LDR R1, = 0x00000000 @ phycontrol2 DLL parameter setting
67. STR R1, [r0, # dmc_phycontrol2]
68.  
69. # Endif
70. /************ DLL initialization-end *************/

 

In step 1, note that for DDR2, the last three digits after phycontrol1 are 0x110;

Step 2:

 

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1. // LDR R1, = 0x0ff01010 @ auto refresh off
2. LDR R1, = 0x0ff01010 // added S
4. STR R1, [r0, # dmc_concontrol]
7. // LDR R1, = 0x00102100.
8. LDR R1, = 0x00212400 // added by S
10. STR R1, [r0, # dmc_memcontrol]
15. LDR R1, = 0x20f00313 // 1cs 256mb0
16. STR R1, [r0, # dmc_memconfig0]
19. LDR R1, = 0x40f00313 // added by S
21. STR R1, [r0, # dmc_memconfig1]
24. LDR R1, = 0x20000000
27. STR R1, [r0, # dmc_prechconfig]
30. LDR R1, = 0x00100004 @ pwrdnconfig
31. STR R1, [r0, # dmc_pwrdnconfig

 

In step 2, it should be noted that for DDR2 and s5pc100, it should be noted that it is related to the actual memory circuit design. I am a 32-bit Parallel storage, so DDR2 corresponds to a CS of 256 MB, therefore, for dmc_memconfig0, chip_mask is F0. If f8. after uboot is used to boot the kernel, the memory configuration of the kernel will die;

There is also a part:

Whether the settings here can affect power consumption is still to be tested.

Step 3:

 

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1. /*********** Timing optimization *************/
3. /************ Ddr2_166mhz *************///
6. // 7.8us * 166 MHz = 0x50e
7. LDR R1, = 0x0000050e
9. STR R1, [r0, # dmc_timingaref]
11. LDR R1, = 0x16233288 // added bu s
12. STR R1, [r0, # dmc_timingrow]
16. LDR R1, = 0x23250304 @ timing data // added bu s
17. STR R1, [r0, # dmc_timingdata]
19. LDR R1, = 0x06c80232 @ timing power !!!!!!!!!!!!!!!
20. STR R1, [r0, # dmc_timingpower]

 

This part should be set based on your memory timing, similar to other boot memory timing configurations.

Step 4:

 

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1. /* Direct command for lpddr-* // added by S 2010.9.16
2. /* Chip0 */
4. LDR R1, = 0x07000000 @ chip0 deselect
5. STR R1, [r0, # dmc_directcmd]
7. LDR R1, = 0x01000000 @ chip0 pall
8. STR R1, [r0, # dmc_directcmd]
10. LDR R1, = 0x00020000 @ chip0 emrs2
11. STR R1, [r0, # dmc_directcmd]
13. LDR R1, = 0x00030000 @ chip0 emrs3
14. STR R1, [r0, # dmc_directcmd]
16. LDR R1, = 0x00010400 @ emrs1 (mem dll on, dqs # disable)
17. STR R1, [r0, # dmc_directcmd]
20. LDR R1, = 0x00000552 @ chip0 Mrs (mem dll reset)
21. STR R1, [r0, # dmc_directcmd]
23. LDR R1, = 0x01000000 @ chip0 chip0 pall
24. STR R1, [r0, # dmc_directcmd]
26. LDR R1, = 0x05000000 @ chip0 chip0 Refa
27. STR R1, [r0, # dmc_directcmd]
30. LDR R1, = 0x05000000 @ chip0 chip0 Refa
31. STR R1, [r0, # dmc_directcmd]
34. LDR R1, = 0x00000452 @ chip0 Mrs (mem dll unreset), BL = 4, CL = 5
35. STR R1, [r0, # dmc_directcmd]
37. LDR R1, = 0x00010780 @ chip0 emrs1 (OCD default)
38. STR R1, [r0, # dmc_directcmd]
41. LDR R1, = 0x00010400 @ chip0 emrs1 (OCD Exit)
42. STR R1, [r0, # dmc_directcmd]
43. /* Chip1 */
44. LDR R1, = 0x07100000 @ directcmd chip1 deselect
45. STR R1, [r0, # dmc_directcmd]
47. LDR R1, = 0x01100000 @ directcmd chip1 pall
48. STR R1, [r0, # dmc_directcmd]
50. LDR R1, = 0x00120000 @ directcmd chip1 emrs2
51. STR R1, [r0, # dmc_directcmd]
53. LDR R1, = 0x00130000 @ directcmd chip1 emrs3
54. STR R1, [r0, # dmc_directcmd]
56. LDR R1, = 0x00110440 @ directcmd chip1 emrs1 (mem dll on, dqs # disable)
57. STR R1, [r0, # dmc_directcmd]
59. LDR R1, = 0x00100552 @ directcmd chip1 Mrs (mem dll reset) Cl = 5, BL = 4
60. STR R1, [r0, # dmc_directcmd]
62. LDR R1, = 0x01100000 @ directcmd chip1 pall
63. STR R1, [r0, # dmc_directcmd]
65. LDR R1, = 0x05100000 @ directcmd chip1 Refa
66. STR R1, [r0, # dmc_directcmd]
68. LDR R1, = 0x05100000 @ directcmd chip1 Refa
69. STR R1, [r0, # dmc_directcmd]
71. LDR R1, = 0x00100452 @ directcmd chip1 Mrs (mem dll unreset)
72. STR R1, [r0, # dmc_directcmd]
74. LDR R1, = 0x00110780 @ directcmd chip1 emrs1 (OCD default)
75. STR R1, [r0, # dmc_directcmd]
77. LDR R1, = 0x00110400 @ directcmd chip1 emrs1 (OCD Exit)
78. STR R1, [r0, # dmc_directcmd]
79. /*************************** End *********** ***********************

 

Now that two slice selections are used, configure the two slice selections.

Step 5: Start the DMC.

 

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1. // [5. Start the DMC.] // added by S
4. LDR R1, = 0x0ff020b0 // change s @ concontrol auto refresh on
5. STR R1, [r0, # dmc_concontrol]
6.  
7. # If 0
8. LDR R1, = 0x001000ff @ pwrdnconfig
9. STR R1, [r0, # dmc_pwrdnconfig]
10. # Endif
15. LDR R1, = 0x00212413 // change s @ memcontrol
16. STR R1, [r0, # dmc_memcontrol]
18. B exit_cpu_init

 

Start DMC

Here the process is basically over, because onenand is not used, so some do not need to pay attention to it temporarily

After testing, uboot can boot the entire kernel and file system normally.

However, I have a question:

I have eight banks, but it's okay if I select two chips. For now, changing it to 0x00 seems the same .. This is a bit dizzy ~

Leave some questions ~ Wait until you start chatting ~