Understanding the MIPI Protocol

after the MIPI signal channel assignment is completed, the timing and synchronization signals that are connected to the physical layer are generated:
MIPI regulation, in the transmission process, the package is 200mV, the package and the package start and the end of the package is 1.2V, two different voltage swing, two different LVDS drive circuits need to switch between the work, in order to transfer the data packets between the safe and reliable transition, From start-up to data transfer, MIPI defines a long and reliable transition time, plus a minimum of more than 600 NS, and specifies that each time parameter is adjustable, so a certain wait time is required, cache is needed, we use registers instead of FIFO, 128Byte per channel.
the transition time between the serial clock and the data differential transmission is as follows:

each time parameter needs to meet the following requirements:



the value of the UI:

The phase relationship of the data to the clock:

According to the previous article: MIPI differential signaling principle (differential signal must be two, comparable, two signal physical characteristics have been, this can guarantee the external interference has been, achieve the same high, with low, but the difference between the two) is introduced.
When the CLKP is high and the clkn is low, the differential signal behaves high.
When the clkn is high, and the CLKP is low, the differential signal behaves as a low level.
So the result can be equivalent to the sine of the red line description.
As can be seen from the sine, data is transmitted at both the high and low levels of CLK.

control of the data channel entry and exit SLM (that is, sleep mode):

MIPI signal transmission is divided into single-ended and differential transmissions. For example:
LP-00, LP-01, LP-10, LP-11 (single-ended)
HS-0, HS-1 (differential)
The Ultra-low Power state entry command:00011110 is a differential transmission, and the Read method is the same as the CLK mentioned above, and it is important to note that the DP and DN are invalid if they are both high or low. This time probably corresponds to the clk sine peak, only one of which is the high one is low is the effective differential data.

Summary :
Corresponds to synchronous signal completion and string conversion;
*HS state is high-speed and low-voltage differential signal, transmitting high-speed continuous serial data;
The *LP state is low-power signal, Transmission control signal and status signal.
*MIPI requires HS to work at a frequency of 1GHz, to complete the common mode signal is 0.2V differential mode signal 0.2V differential
Transmission of signals ;
*LP Transmission Control signal, requires a high level of 1.2v low level of 0 level signal output;
*HS and LP State, the electrical characteristics of the output signal is very demanding, the specific electrical performance requirements can be seen
Attached document table.
*mipi is two-way optional, can be sent at high speed, can also be high-speed reception, or transceiver function at the same time,
We are currently only sending functions on demand;

*mipi HS Mode (0.2V), transfer image data, speed of 80Mbps ~ 1000Mbps;
The *MIPI LP mode (1.2V) can be used to transmit control commands at a maximum speed of 10Mbps;

*mipi stipulates that any MIPI device must escape Mode, which is low Power Data
One of the trabsmission MODE,LP modes, in which images or other data can be transmitted at low speeds.

The *MIPI specifies the voltage range of low power mode, Ultra low power mode, and their
Between them and the HS mode or related requirements;

*mipi d-phy is a physical layer specification shared by each MIPI working Group;
Finally, one thing to note:
Bta:bus turn around, used by the host to accept the peripheral Send command or response signal, if the host dphy set this,
But if the LCD doesn't support it, there may be a problem.

Understanding the MIPI Protocol