Understanding the spatial structure of Windows PCIe devices with WindRiver

This paper mainly through the WindRiver tool graphical view PCIe device, to understand the space structure of PCIE devices. This article mainly refers to the "PCI Express Architecture Guide" and the Netizen blog: Click to open the link.

I. The space structure of PCIE equipment

PCIe devices have three separate physical address spaces: device memory space (memory), IO space, and configuration space (config). Because the PCIe device supports Plug and Play, the memory space and IO space are the base addresses that the operating system determines its mappings after the device is plugged into the host. Refer to the code for Microsoft plx9x5x:

    Parse the resource list and save the resource information. for (i=0; i < Wdfcmresourcelistgetcount (resourcestranslated); i++) {desc = Wdfcmresourcelistgetdescriptor        (resourcestranslated, I); if (!DESC) {traceevents (Trace_level_error, Dbg_pnp, "Wdfresourcecmgetdescriptor failed")            ;        return status_device_configuration_error;                } switch (desc->type) {case cmresourcetypememory:bar = NULL;                    if (Foundsram &&!foundsram2 && desc->u.memory.length = = 0x400000) {                    Sram2basepa = desc->u.memory.start;                    Sram2length = desc->u.memory.length;                    foundSRAM2 = TRUE; Bar = "BAR2";                Kdprint (("BAR2 found.\n"));            } if (Foundregs &&!foundsram && desc->u.memory.length = = 0x400000) {         Srambasepa = desc->u.memory.start;                    Sramlength = desc->u.memory.length;                    Foundsram = TRUE; Bar = "BAR1";                Kdprint (("BAR1 found.\n")); } if (!foundregs && desc->u.memory.length = = 0x1000) {reg                    Sbasepa = desc->u.memory.start;                    Regslength = desc->u.memory.length;                    Foundregs = TRUE; Bar = "BAR0";                Kdprint (("BAR0 found.\n")); } traceevents (Trace_level_information, Dbg_pnp, "-Memory Resource [%i64x-%i64x ]%s ", Desc->u.memory.start.quadpart, Desc->u.memory.start.qua Dpart + desc->u.memory.length, (bar)? Bar: "<unrecognized>"); Kdprint ("Desc->u.memory.start is%x, Desc->u.memory.length is%x\n", Desc-> U.memory.start, desc->u.memory.length));            Break                Case Cmresourcetypeport:bar = NULL;                    if (!foundport && desc->u.port.length >= 0x100) {foundport = TRUE;                Bar = "Port"; } traceevents (Trace_level_information, Dbg_pnp, "-Port Resource [%08i64x-%08 I64x]%s ", Desc->u.port.start.quadpart, Desc->u.port.start.qua Dpart + desc->u.port.length, (bar)? Bar: "<unrecognized>");                Kdprint (("Cmresourcetypeport is found.\n"));            Break        Default:////Ignore All and descriptors//break; }} if (! ( Foundregs && Foundsram) {traceevents (Trace_level_error, Dbg_pnp, "plxmapresources:missing resources ");    return status_device_configuration_error; }

Configuration space is critical for device control. The PCIe device supports 256 bytes of configuration space, the most basic being the first 64 bytes, such as:

Second, WindRiver

1, Memory space

The device maps a total of 6 memory spaces, of which the first block is 4kB and the 5 blocks behind it are 32MB. You can also see the same results in Device Manager for Windows Heavy.

2, configure the space

Understanding the spatial structure of Windows PCIe devices with WindRiver