USB Full speed/high speed device identification signal analysis __USB

The following content is reproduced from the USB chirp signal test, in this article explains in detail the USB high-speed device handshake process, and through the analysis d+ and D-above waveform to explain. It's a great article. First, Chirp K-J Signal Description

The USB chirp signal is divided into k signal and J signal. Depending on the USB rate, the chirp signal is distinguished as follows:
Second, the USB full speed high-speed identification process analysis

According to the specification, full Speed and low-speed (Low Speed) are well differentiated. Because there is a 1.5k pull resistor on the device side, when the device is plugged into the hub or power (fixed cable USB device), the cable with the pull resistor will be pulled high, the hub based on the d+/d-level to determine whether the device is mounted at full speed or low-speed equipment.

USB full/Low speed recognition is quite simple, because usb1.x is a pair of data lines, in USB2.0 can not be as full/low speed as the data line on the pull resistance position to recognize the USB third speed-high-speed. Therefore, the recognition of high-speed equipment is slightly more complicated.

The high speed device was initially identified as a full speed device, which, like a full speed device, had a 1.5k pull resistor on the d+ line. USB2.0 's hub treats it as a full speed device, after which the hub and the device confirm both identities through a series of handshake signals. In this case, the speed of the detection is two-way, such as the high-speed hub needs to detect the equipment hanging up is high speed, full speed or low speed, High-speed equipment needs to detect the hub is USB2.0 or 1.x, if the former, on a series of action cut to high-speed mode of work, if the latter, to full speed mode of work.

When the hub detects the insertion/power-on of a device, it informs the host that the host sends the SET_PORT_FEATURE request for the hub to reset the newly inserted device. The device reset operation is the hub through the drive data line to the Reset state SE0 (single-ended 0, i.e. d+ and D are all low levels), and lasts at least 10ms.

The high speed equipment sees the reset signal, through the internal current source to the D-line continuous irrigation size of 17.78mA current. Because at this time the high-speed equipment of the 1.5k pull resistance has not been revoked, at the hub end, full/low-speed drive to form an impedance of 45 ohms (OHM) of the terminal resistor, 2 resistors in parallel is still about 45 ohms impedance, so at the hub end to see a voltage of about 800mV (45 ohms *17.78ma) , this is the chirp K signal. The duration of the CHIRP K signal is 1ms~7ms.

At the hub end, although the reset signal, and has been driven by the SE0, but USB2.0 high-speed receiver has been in the detection chirp K (d+ bit 0,d-1) signal, if not see chirp K signal, continue to reset operations, until the end of the reset, and then in full speed mode operation. If the hub is only a full speed and does not support high-speed operation, then the hub ignores the chirp K signal sent by the device, and the device does not switch to high-speed mode.

After the chirp K signal is sent by the device, the hub must begin to reply to a series of kjkjkj ... sequence, indicating to the device that this is a USB2.0 hub. The KJ sequence here is continuous, the middle is not interrupted, and the duration of each k or j is between 40us~60us. After the KJ sequence stops, the 100~500US ends the reset operation. The hub sends the chirp KJ sequence in the same way as the device, through the current source to the differential data line alternating 17.78mA of current implementation.

Go back to the device. When the device detects a chirp signal from 6 hub (3 pairs of KJ sequences), it must switch to high-speed mode within 500US. The toggle action has: Disconnect the 1.5k pull resistor, the high speed terminal resistor (high-speed termination) connected to the d+/d-, is actually the full speed/low-speed differential drive, and enters the default high speed state. After performing 1, 22 steps, the phenomenon that is seen on the USB signal line changes: The chirp kj sequence amplitude sent out by the hub drops to the original half, 400mV. This is because the device to mount a new terminal resistor, with the original hub end of the terminal resistor, parallel impedance is 22.5 ohms. 400mV is from 17.78ma*22.5ohm. In the future, the signal amplitude of high-speed operation is 400mV instead of 3V as full/low speed.

At this point, high-speed equipment and the USB2.0 hub shook hands, followed by 480Mbps high-speed signal communication. third, signal testing and judgment considerations

High-speed detection handshake negotiation is in the host issued reset (reset) signal, initiated by the device, by the host response process;

After the host uses the SE0 state reset device, it is necessary to use the high-speed handshake negotiation (chirp handshake) to communicate normally again.

When the host uses the full speed idle state suspend device, it needs to get the equipment into working state through the resume process, this process does not need the high-speed handshake negotiation;

In full/low speed mode, the host resume device is maintained at the High speed Terminal mode by maintaining the K state 20ms, the 20ms K state at high speed to convert to SE0 state, and then the host and the equipment must be kept in the high-speed terminals in the two times of Low-speed bit (2 low speed bit times);

Device_remote_wakeup feature, which is used when the device is suspended (suspend), the host can use the resume signal to wake the device. This feature is set up and cleared by the host using set_feature and clear_feature request pairs. Four, USB chirp signal Test table

In the measured process, the yellow waveform is d+, the green corresponds to D- 1, and the circuit based on high speed transmission

2. High-speed synchronous mode

The synchronous mode is shown in the red circle of the second half of the measured waveform and is the normal waveform. 3, high-speed speed detection

such as the measured waveform, the picture above is the overall waveform, the image below is the enlarged part of the red circle above, visible: The module is exited idle (2.9V left-right level) mode 1.5ms; First d on the issue of a continuous 2ms of chirp K signal (800mV level); host reply chirp JK Sequence (800mV level) device after receiving the disconnect 1.5K pull resistor, waveform assignment reduced by half (400mV level);

The 2nd step above is the device to inform the host itself is a high-speed device, the 3rd step is the host response device notification, the 4th step level assignment to halve the success of the negotiation, the implementation of synchronous action. 4, host reset equipment