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A OHCI Drive Frame

Two Data structure of OHCI

Three Initialization of the HCD

Four OHCI related Code

The purpose of OPENHCI (Open Host Controller Interface) is-accelerate the acceptance of USB in the marketplace by promo Ting the use of a common industry software/hareware interface.

A OHCI Drive Frame

The following figure illustrates the USB device Driver,host controller driver and the hardware host controller,

The relationship between USB device

Between the host controller and host controller driver, there are two communication channels.

A channel is a series of operable registers that reside on the host controller, and the target of the channel is

Host controller. This series of registers includes the control, the state, and the list pointer register.

The other channel is HCCA (host controller communication area) Hcca a piece of shared memory,

The data communication of the channel is initiated by the host controller, which eventually passes it to the driver. HCCA includes the interrupt endpoint descriptor chain header, the end queue's linked header, and the status information associated with the start frame.

The following image is the classic channel diagram for OHCI,

For host controller driver, its responsibilities include host Controller Management,

Bandwidth Allocation, list Management, root hub (root hub is integrated in HC, so it can be set by HCD). Frames in bandwidth allocation that refer to 1ms are used to transmit data. Whenever a SOF is produced, HC starts transmitting a frame of data.

For the host controller, its responsibilities include, USB states,frame management,list processing (here the done queue through HCCA has HC to HCD)

Two Data structure of OHCI

Data structures in OHCI include TD (Transfer Descriptor) and Ed (Endpointer descriptor)

Ed contains the necessary information for the host controller to communicate with the endpoint, including the maximum packet length, the endpoint address, the transmission speed of the endpoint, and the direction of the data flow.

Ed's headp is the head pointer of the TD linked List, TAILP is the tail pointer, nexted is the next ed pointer (these settings can also be seen from the second part of the graph, are DWORD)

The HWInfo is passed by a variable pipe, where

Fa:function Address


D:direction in off direction from TD

S:speed full-speed s=0 low-speed S=1

K:skip when this bit is set, HC skips this ED

F: If this bit is 0, indicate using the general TD format otherwise use isochronous TD format


h:halted this bit was set by the HC to indicate that processing of the TD queue on the endpoint is halted

C:toggle carry this bit is the data toggle Carrry bit

TD contains the necessary information for packet transmission, including data toggle,shared memory buffer location and completion status codes.

General Transfer Descriptor Format (BULK/CONTROL/INTERRUPT)

Cbp:currentbufferpointer contains the physical address of the the next memory location that would be a accessed for transfer to/ From the Endpoint

Nexttd:next TD

Be:buffer end contains physical address of the last byte in the buffer for this TD

Cc:condition Code

Ec:error count for each transmission error,this value is incremented

T:data Toggle

For Bulk/control Ed List, whose hptr is located in a register on HC, interrupts the ED list, Hptr is saved in Hcca, and when Ed Hptr connects to the last interrupt Ed

Three Initialization of the HCD

There is a number of steps necessary for the OS to bring it Host Controller Driver to an operational state:

Load Host Controller Driver and locate the Hc

Verify the HC and allocate system resources

Take control of HC (can not)

Set up HC registers and HCCA

Begin sending SOF tokens on the USB

The first 3 steps have been completed in Hc_start, and the 4th step after filling the ED,TD related registers can be

Proceed to step fifth. Some of these parameters are configured, such as frame frequency set to 1MS,HC from suspend to resume time at least 2ms, interrupt enable SOF interrupt, Hcperiodicstart value is 90%*frameinterval, etc.


If Controlbulkserviceratio field is set to 4:1, then control Ed and bulk ed in one frame

Is 4:1, and the host controller enforces the control Bulk Service Ratio Regardless of the number of control and Bulk End Point descriptor present on their respective lists. If there is a 1 control Endpoint descriptor on the control list and the control Bulk Ratio is 4:1,that control Endpoint Descriptor is serviced 4 times before a Bulk Ed is serviced.

List Enabled Check

If the list is enabled, the host controller may service the list. If the list is disabled,the Host controller skips, then list and moves on to the next list. The order of service for list can be obtained by OHCI documents.

Four OHCI related Code

For OHCI, the specific to Code section is primarily in the function submit_common_msg, which is ultimately called by the following function

And Usb_control_msg is called by most of the enumeration process-related functions

The enumeration process for the specific root hub is implemented in Ohci_submit_rh_msg, and the OHCI-related

Number of submit_common_msg. The function mainly calls two functions, one is sohci_submit_job and the other is hc_interrupt.

A) Sohci_submit_job

The Sohci_submit_job invocation situation is shown in the following figure

AA) ep_add_ed

The function is to initialize a ed_t *ed, which is stored in the corresponding ohci_dev.ed[], and the array corresponding subscript is determined by the transport type. If an ED of type 4 is used for the first time, it is initialized (including creating dummy TD, Link dummy TD), otherwise only the hwinfo of the ED is set (that is, the first two words)

AB) Td_alloc

Assign TD, depending on the type of transmission, the number of TD, such as bulk transmission for the 2td,control transmission of 3TD (setup,in,out), the assigned TD placed in the structure purb_priv->td[]




purb_priv->ed=ed; (Ed pointer returned by ep_add_ed)

AC) Ep_link (for example, Pipe_control)

Ep_link is called if Ed->state is not ed_oper. When Ed->state is Ed_unlink, Ed_link is called. The function is to link ed to the chain with the state set to Ed_oper

For Pipe_control, if Ohci->ed_controltail is empty, then the above Ed is written to the Ed_controlhead register, as Ed_control's head Ed, otherwise as the tail ed. Enable Ohci_ctrl_ CLE, redirect Ed_controltail tail pointer

AD) Td_submit_job (cite Pipe_control as an example)

For control transmission, there are at least 2 TD, the first must be the setup package (corresponding to length 8), TOGGLE=TD_T_DATA0, the rest of the toggle=td_t_data1, call Td_fill to connect these TD to the corresponding ED. These TD may be in or out or both, determined by Trans_len and pipe

The same first DWORD is hwinfo in the code

According to the second part of the figure, we can write a good td_fill function, nothing but the operation of the list

Finally, if OHCI is not dormant within the function, the

Writeln (Ohci_clf,&ohci->regs->cmdstatus), start control list

(See Cmdstatus Register for details)

b) Hc_interrupt

Wait for transmission to end, HCCA related interrupts

In the function Hc_interrupt, the main processing class three interrupts, respectively, is writeback of Done_head,start Frame,overrun, for the latter two are closed after the interruption, re-open interrupt (if necessary), and writeback of Done_ Head adds one more function dl_done_list (&gohci,dl_reverse_done_list (&GOHCI))

Since TD is transmitted to don_head with a FIFO base address, it is necessary to flip td_list, which is the function dl_reverse_done_list, and Dl_done_ List is to check whether all TD successfully transmitted (according to the number of TD transmitted and the number of received, if the transmission is successful), and finally call Ed_unlink to remove the corresponding Ed from the Hptr

Five Summary above is u-boot in the OHCI introduction, mainly on the control transmission has a more detailed introduction, especially the ISO transmission is not a special understanding, need to further study.

Transferred from:

Another article about the OHCI of the understanding of the process of data transmission, has a certain reference significance:

Transferred from:

The s3c2440 provides a USB host interface that is fully compatible with the OHCI v1.0. To use this feature, you must familiarize yourself with the OHCI v1.0 specification, and you must familiarize yourself with the USB v1.1 protocol before you are familiar with the OHCI v1.0 specification. Therefore, it is not an easy task to use the USB host interface provided by s3c2440 if it involves more content in this part. Here, I mainly introduce the USB device enumeration process involved in some of the knowledge, and give a concrete implementation of the program.

OHCI (Open HCI) is one of the three most widely used USB host controller specifications available. The USB architecture is comprised of four main components: Customer software/USB driver, host controller driver (HCD), host controller (HC) and USB drive. The first two are implemented by software, and both are implemented by hardware. The OHCI is the interface between the host controller driver and the host controller, and their basic operation. Between the host controller driver and the host controller, there are two communication channels, the first one is the application of a set of operational registers located in HC, which includes the control register, the status register and the list pointer register, and the other channel is to apply the shared memory called Host controller Communication domain (HCCA).

USB defines four types of data transfer: Control transmission, bulk transfer, interrupt transmission, and synchronous transmission. In the OHCI specification, data transmission types are divided into two categories: periodic and non-periodic transmissions. Synchronous and interrupted transmissions are periodic transmissions, and control transmissions and bulk transmissions are non-periodic. USB defines a period of 1.0 milliseconds per frame, in order to ensure that each frame can occur periodic transmission and non-periodic transmission, generally, ohci the bandwidth of each frame is divided into four parts, the first is to send SOF, and then the non-periodic transmission, followed by periodic transmission, if the period of transmission is complete, there is time, the remaining time is still left to

The endpoint descriptor (ED) and Transport descriptor (TD) are the two most basic communication modules. Ed contains information about an endpoint that is used by HC to manage the use of endpoints. The typical parameters of Ed include endpoint address, transfer speed, maximum packet size, and Ed also provides a stop (anchor Point) for the TD list. TD is an ED-dependent memory buffer that is used to transfer data between endpoints. When HC accesses an ED and finds a valid TD address, HC completes a simple transfer task with the endpoint, which is determined by Ed and the data memory address that is accessed is specified by TD. When all the data transmissions defined by TD are complete, TD is decoupled from Ed and linked to the completion list. This completion list can be handled by HCD to provide some completion information.

The data structure of the ED is 16 bytes long, and its fields are:

function address of FA:USB;

The endpoint address within the EN:USB function;

D: The transmission direction of data flow, is in,out, or have TD to determine the direction of transmission;

S: velocity, full speed or low speed;

K: Used to set skip current Ed;

F: The TD form linked to Ed, is the general TD format or synchronous TD format;

MPS: Maximum byte size for data transfer;

The tail pointer of the TAILP:TD list;

H: Used to stop the processing of the current TD list;

C: Data rollover carry bit;

HEADP:TD the head pointer of the list;

Nexted: The next ed pointer to be processed.

Based on the above instructions, we can define ED as the following data type:

typedef struct _ED {

volatile unsigned int Control;

volatile unsigned int tailp;

volatile unsigned int headp;

volatile unsigned int nexted;

} ED, *p_ed;

Since Ed must be a 16-byte address alignment, we must declare its variables in the following form:

__align (+) Ed Ed;

We can use the following function to create an ED:

__inline void Createed (

unsigned int edaddr,//ed address pointer

unsigned int maxpacket,//mps

unsigned int tdformat,//f

unsigned int Skip,//k

unsigned int speed,//s

unsigned int Direction,//d

unsigned int endpt,//en

unsigned int funcaddress,//FA

unsigned int tdqtailpntr,//TAILP

unsigned int tdqheadpntr,//HEADP

unsigned int togglecarry,//c

unsigned int nexted)//nexted


p_ed PED = (p_ed) edaddr;

Ped->control = (maxpacket << 16) | (Tdformat << 15) | (Skip << 14) | (Speed << 13)

| Direction << 11) | (ENDPT << 7) | funcaddress;

Ped->tailp = (Tdqtailpntr & 0xfffffff0);

PED->HEADP = (tdqheadpntr & 0xfffffff0) | (Togglecarry << 1);

ped->nexted = (nexted & 0xfffffff0);


TD is a total of two types: general TD and synchronous TD. Universal TD is used for interrupt, control, and batch endpoints, and synchronous TD is used for synchronous transmission. Here, we only give the data structure and definition of universal TD.

The data structure of the universal TD is also 16 bytes, and its fields are:

R: Cache rounding, to set whether the length of the last packet needs to be the same as the length defined;

DP: Direction, is in,out, or setup;

DI: Delay interrupt;

T: Data rollover;

EC: Transmission error count;

CC: Condition code, for the state of the last attempted transmission;

CBP: The physical address of the data memory that will be transmitted;


BE: The physical end byte address of the data memory that will be transmitted;

Based on the above instructions, we can define a generic TD for the following data types:

typedef struct _TD {

volatile unsigned int Control;

volatile unsigned int CBP;

volatile unsigned int nexttd;

volatile unsigned int be;

} TD, *P_TD;

Since universal TD must be a 16-byte address alignment, we must declare its variables in the following form:

__align (+) TD td[4];

We can use the following function to create a generic TD:

__inline void Creategentd (

unsigned int gentdaddr,//TD address pointer

unsigned int datatoggle,//t

unsigned int delayinterrupt,//di

unsigned int Direction,//DP

unsigned int bufrnding,//r

unsigned int curbufptr,//CBP

unsigned int nexttd,//NEXTTD

unsigned int bufflen)//Transmitted data length, which can be obtained by this variable


P_td PTD = (P_TD) gentdaddr;

Ptd->control = (datatoggle << 24) | (Delayinterrupt << 21)

| (Direction << 19) | (bufrnding << 18);

PTD->CBP = curbufptr;

PTD->NEXTTD = (Nexttd & 0xfffffff0);

Ptd->be = (bufflen)? Curbufptr + BuffLen-1: curbufptr;


Here we give the HCCA data structure, which is 256 bytes long, including 128 bytes of HCCA interrupt table, 2 bytes of Hcca frames, 2 bytes of Hcca Note (indicates whether HC is updating HCCA frames), 4 bytes of Hcca complete queue header pointer, and 116 bytes of reserved area. Based on the above instructions, we can define HCCA as the following data type:

typedef struct _HCCA {

volatile unsigned int hccainterrupttable[32];

volatile unsigned short hccaframenumber;

volatile unsigned short HccaPad1;

volatile unsigned int hccadonehead;

Volatile unsigned char reserved[116];

} Hcca, *p_hcca;

Since HCCA must be a 256-byte address alignment, we must declare its variables in the following form:

__align (HCCA) Hcca;

OHCI is a specification of the USB host controller based on the register layer description, so HC contains some on-chip operational registers that can also be used by HCD. Below we will briefly introduce the registers in the OHCI.

HCREVISION:HCI specification version;

HCCONTROL:HC mode of operation, cbsr--in the non-periodic queue, the ratio of the controlled Ed to the batch ed, cle--the next Frame Control queue processing Enable, HCFS--USB Host controller function status, including reset, restart, operation and abort;

HCCOMMANDSTATUS:HC Receive to HCD command, also can reflect the current state of HC, hcr--software reset hc;clf--Determine if there is a control queue TD;

Hcinterruptstatus: Provides various states that can trigger a hardware interrupt event;

Hcinterruptenable: Enables a bit to be used to control the generation of hardware interrupt events;

Hcinterruptdisable: Invalid for controlling bits that produce a hardware interrupt event

The physical address of the Hchcca:hcca;

Hcperiodcurrented: The physical address of the current synchronization or interrupt Ed;

Hccontrolheaded: The physical address of the first Ed that controls the queue;

Hccontrolcurrented: The physical address of the current control opposite Ed;

Hcbulkheaded: The physical address of the first Ed of a batch queue;

Hcbulkcurrented: The physical address of the current batch-opposite Ed;

Hcdonehead: The physical address of the nearest TD that was added in the completion queue;

Hcfminterval: Contains a 14-bit fi--used to denote the bit time occupied within a frame, 2 consecutive sofs, and a 15-bit psmps--used to indicate that the maximum packet size can be sent or received at full speed without raising a dispatch overflow, the recommended value for Fi,psmps is 0x2edf and 0x2778.

The inverted counter of the hcfmremaining:14 bit to indicate the time remaining for the current frame;

Hcfmnumber:16 bit counter to provide timing reference;

HCPERIODICSTART:14-bit programmable values to determine when HC starts the execution of the cycle queue;

A hclsthreshold:11-bit value that determines whether the maximum 8-bit LS packet transmission is performed prior to EOF;

Hcrhdescriptora: The first register to be described with a hub;

Hcrhdescriptorb: The second register that is described with a hub;

Hcrhstatus: Includes hub state domain and hub State change field;

HCRHPORTSTSTUS[1:NDP]: For controlling and reporting events on each port, in s3c2440, NDP is 2

The following gives the initialization of the OHCI, which are all based on registers. According to the OHCI specification, HCD should complete the following initialization steps:

Initializing the HCCA Data memory unit

Initializes an operational register to match the current device data state

Set Hchcca

Set hcinterruptenable

Set Hccontrol

Set Hcperiodicstart

In conjunction with the actual content described in this article, the OHCI initialization function is:

void Ohciinit ()


unsigned int fminterval;


Rhccontrol = 0;

Write Hcca

Rhchcca = (volatile unsigned) &hcca;

Set frame interval

Fminterval = 0X2EDF;

Rhcfminterval = (((((fminterval-210) * 6)/7) << 16) | Fminterval;

Rhcperiodicstart= (Fminterval * 9)/10;

Initialize Hcdonehead

Rhcdonehead = 0x00;

Hcca. Hccadonehead = 0x0000;

Set HC to run state

Rhccontrol = 0x80;


The process of identifying a host to a USB device is called a device enumeration, so enumeration is critical for USB. In this article, only the following simple 5-step enumeration process is performed:

1, host requirements to get device descriptor, Setup packet: 0x80, 0x06,0x00,0x01,0x00,0x00,0x40,0x00, the maximum data length is 0x40;

2, the second setup package is to assign an address to the device, the content is generally: 0x00,0x05,0x02,0x00,0x00,0x00,0x00,0x00. 02 of these means that the address assigned to the device is 0x02, we can only use the 0X02 value when we operate on the device.

3, the host with a new address to obtain the device descriptor again, the setup package is: 0x80,0x06,0x00,0x01,0x00,0x00,0x12,0x00, and the last time, the data length of the actual data length 0x12;

4, the host reads the device all configuration descriptor, the setup package is: 0x80,0x06,0x00,0x02,0x00,0x00,0x40,0x00, because the host does not know

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