Using Makefile (ii)----compilation under Windows

It is necessary to set the "need to execute =" "Mspdb60.dll, and it is installed in the =" "c:\msdev\common\msdev98\bin=". <= "" P><p> If you write the program is not just a simple = "" program, but also used = "" MFC, the same can be in the = "" console= "" mode= "" "compile, this time your environment variables should be set: <=" "mfc\ Include= "" and = "" Mfc\lib, you can let the compiler and the linker find = "" mfc= "" = "libraries. If you still need to use the = "" ATL, you have to add = "" in the environment variable = "C:\msdev\vc98\atl\include. <= "files\microsoft=" "studio, so rewrite the batch file as follows: <=" "studio\vc98\bin;d:\program=" "studio\common\msdev98\bin=" " Studio\vc98\include;d:\program= "" Studio\vc98\mfc\include= "" studio\vc98\lib;d:\program= "" Studio\vc98\mfc\lib <= "" P><p> then run cmd to copy and paste the above settings to the mouse blink. If you want to make sure that the path changes correctly, you can type the set command to view. <= "" p><p> Note: Such an environment variable modification is only valid for this command-line window because it is a virtual device. Do not do this work if you want to enter it every time. You can run Vcvars32.bat and set up your environment variables. In order not to affect the original set of VC + + to facilitate the use of integrated environment, I do not actually operate, a simple copy and paste is not necessarily troublesome. It can also be modified directly in My Computer-Properties-advanced-environment variable, which is also permanent. Here, the path is set. Here's a try: <= "" P><p> I saved a test.cpp file as a test file on the f:\ disk. The contents of the file are as follows: <= "" #include = "" <iostream.h>= "" void= "" main () = "" {= ""  cout<< "Hello" <<endl;= "}=" ========================================

The

uses the CD command to switch the current command-line window path to F:\>, and then executes the CL "Test.cpp command, generating two files, Test.obj, and Test.exe under the f:\ disk path. Then run Test.exe, and you'll see the results (output Hello). <= "" p><p> below to give an example, that is, the following to learn the makefile file. The test file is named Mypath.mak (you can name any) and is still stored under the current path. <= "" all:  = ""  = "" @echo   = "" $ (path) = "=========================

Run the command nmake "Mypath.mak, you can see the output as the path you just set (my result is d:\program=" "studio\common\msdev98\bin). <= "" p><p>2. Generate your own makefile file <= "" P><p> here is a simple example I found on the internet and its commentary (<a= "target=" _blank "href=" Http://www.readygo.com.cn/it-1104697.html ">http:=" "www.readygo.com.cn=" "it-1104697.html<=" "a>" <= "" Here is a simple example (the following are examples of the Win32 platform):   = "" File name: makefile  = "" 1.  = "" #  = "" makefile  = "2.  =" "this  =" "is  =" "a  =" "example   = "of  =" "make  =" "file  =" "3.  =" "all:a1  =" "a2   = "" 4.      = "" all!  = "" 5.  = "" a1:  = "" 6.       = "" a1!  = "" 7.  = "" a2:  = "" 8.       = "" a2!  = ""    = "" "After running make, the results are as follows:   =" "  Now let's examine this simple rule file. =""  = "      =" "1th, 2 lines Needless to say, a glance can be seen as a comment. In the Make rule file, the comment starts with "#", is the line comment, and the "=" "function in C + +. But you can't put it behind other statements, or it's wrong. Line 3rd is the beginning of the rule! All:a1  = "" In the A2 line, the name of the rule is all, which is usually the target name. A rule can have more than one name, like this line, you can also write it all  = "" all2:a1  = "" A2. At this point, the rule has two names-all and All2. Of course, there can be more, all look at yourself. The following 5 and 72 lines are also the beginning of the two rules. After the ":", it is the dependency. In this line, there are two dependencies, namely A1 and A2. These dependencies can be other rule names (target names) or filenames. The relationship between dependency and target is "dependency". In one rule, there can be 0 (as in the following two rules), one or more dependencies. Line 4th @echo  = "" all! is the command line. It is the command to execute when the all rule is executed. Note that a command within a rule starts with a tab line to indicate that the command belongs to a rule. A rule can also have multiple commands, one for each command (to start with a tab). As for which commands you can use, it depends entirely on the OS and shell you use. = "       =" When you perform make, it finds the first rule. Then, make checks the relationship between the dependencies and the target. If the target is older than the dependency, the rule is executed to update the target. Finish executing the rule. How to determine the goals and dependencies of the new and old? If the target (file) does not exist, the target time is 0, and if the target (the file exists), the target time is the modified time of the file. If the dependency is a rule, it executes the dependent rule (here is a recursive), then the time to depend on is the current time, if it is an existing file, it is the file modification time, otherwise the error. After that, you can compare the relationship between the target and the dependency. However, one thing that is special is that when there is no dependency, the time to rely on is 1. = "" In this example, make first finds the rule "all", finds that the target does not exist, so the target time is 0, and then finds the dependent "A1", and the result "A1" does not exist, so the rule "A1" is executed. "A1" does not exist, so it's time for 0, while "A1"There is no dependency, it depends on the time of 1;1>0, so the rule" A1 "is executed. Then return to the rule "all" and then check the dependency "A2". The "A2" execution process is the same as "A1". At this point, the target time for "All" is 0, and the dependent time is the latest time. Then, execute the command "all" of the rule. = "" Of course, you can also specify a rule for make to execute, such as: make  = "" A1 This command is to tell the make program not to find the first rule, but the rule "A1" to execute. And we can execute more than one rule at a time, for example: Execute make  = "" a1  = "A2 will execute" A1 "," A2 "two rules successively.   = "" p><p>     = "" OK, although it is very confusing, but also cost me a half-day strength. You should know a little bit about the execution of make rules.   = "=============================================

The basic wording of the dependency is as follows: "Target:dependence=" "         =" "command<=" " Target can be a file name. The dependence can be a different target name or file name. Commands are the command lines that the operating system runs.   = "" "Variable   =" "     =" "a make rule file with this content is basically working." However, when we compile a program, if some of the content to be used repeatedly, each time to write a long list of words, it is very troublesome. As a result, make introduces the concept of macros (which can actually be seen as a simple scripting language).   = "" Macro variable is defined as follows:   = "" var1  = "  " macro  = "" demo!  = "" VAR1 is the variable name, and its value is "this  =" "demo!"   = "" If we want to use the value of this variable, it is only through the operator-$ (VAR1) represents "this  =" "demo!".   = "" as follows makefile  = "" 3.      = "" $ (var1)   = "" Result output:   = "" A macro variable can also be defined when a user executes a command line. The form is as follows:   = "" "all  =" "var1=" "this  " Test "  =" "Execution Result:   =" "Test   = "" Not only can we use custom variables, we can also use system environment variables in this way. This makes it much easier for us to suggest flexible rules. The following makefile  = "" 2.      = "" $ (windir)   = "" C:\windows= "" (Note: Variables in makefile are case-sensitive)   = "=========================================

Here are some of the built-in variables for the makefile file:

========================================== "[email protected] represents the target name (that is, the rule name) in the rule. = "" $< represents a dependent item in the rule.  Note that it only represents the first item in all dependent projects of the rule!  = "" and others: = "" $^ represents all dependent items in the rule.  = "" $? Represents a dependent project in a rule that is new to the target.  = "" Not only that, but also to add some restrictions to these special variables. = "" such as: = "" in rule = "" debug= "" Out.exe = "": = "" Out.obj = "", [email protected] stands for debug= "" Out.exe, while $ (@d) represents directory name debug,$ (@f ) represents the file name Out.exe.  Other such as $ (<D), $ (<f), $ (^d), $ (^f), $ (? d), $ (? f), are similar. ="============================================

As an example, here is the original makefile file content:

============================================== "myprog=" "foo.o=" "bar.o=" "=" "gcc=" "-o=" "foo.c=" "foo.h=" "bar.h=" "-c=" "bar.c=" "objs=" foo.o "cc=" gcc "cflags="-wall "-g=" "$ (OBJS) =" "$ (cc) =" $^= "" [Email protected]= "" $ (cflags) = "" $& Lt;-o= "" >

Using makefile (ii)----compilation under Windows