Various soft core processor binary files FPGA initialization File Generator program

Whether it is MIPS, Nios II, Microblaze, MSP430, 8051, OpenRISC, OpenSPARC, leon2/leon3, etc. soft core processor, When implemented on an FPGA, we typically need a portion of the on-chip RAM storage bootloader, which can be used with GCC objcopy to bootloader text, exception vector, rodata, data or BSS and so on you need to copy out, you can generate binary files through-o binary, you can use-J. Section to extract the section you want, of course, you can also specify by default the--gap-fill 0x00 parameter blank padding between the sections data. Use the following C program to generate memory initialization data that complies with $READMEMH calls in Altera, Xilinx, and Verilog. The following code can be modified slightly based on the size-to-end pattern of the different processor architectures.

/** This program was free software:you can redistribute it and/or modify * it under the terms of the GNU General publ IC License as published by * The free software Foundation, either version 3 of the License, or * (at your option) any LA ter version. * * This program was distributed in the hope that it'll be useful, * but without any WARRANTY;  Without even the implied warranty of * merchantability or FITNESS for A particular PURPOSE. See the * GNU general public License for more details.  * * You should has received a copy of the GNU general public License * along. If not, see <http://www.gnu.org/licenses/* * Copyright @ Lyu Yang----------------------------2015-10-02*/#include<stdio.h>#include<stdlib.h>intMainintargcChar**argv) {    intI, j, FileLen =0, address =0, maxaddr; FILE* Filein, *fileout; if(ARGC! =3) {printf ("Arguments error!\n"); printf ("\nusage:bin2fpga.exe Depth inputfile\n"); return 0; }    Else{Filein= fopen (* (argv +2),"RB"); if(Filein = =NULL) {printf ("File does not exist!\n"); return 0; } fseek (Filein,0L, Seek_end); FileLen=Ftell (Filein); printf ("\ninput File length is%d bytes.\n", FileLen); Maxaddr= Atoi (* (argv +1)); unsignedChar* BUF = (unsignedChar*)malloc(sizeof(Char)*FileLen); if(BUF = =NULL) {printf ("Memory Allocate error!\n"); return 0; }                //For Altera FPGA MIF fileFileout = fopen ("./ALTERA.MIF","W"); if(Fileout = =NULL) {printf ("Output File Create error!\n"); return 0; } fprintf (Fileout,"DEPTH =%d;\nwidth = 32;\naddress_radix = Dec;\ndata_radix = hex;\ncontent\nbegin\n", MAXADDR); Fseek (Filein,0L, Seek_set); Fread (buf, FileLen,1, Filein);  for(i =0; i < FileLen; i + =4) {fprintf (fileout,"%d:", address); fprintf (Fileout,"%02x", Buf[i +3]); fprintf (Fileout,"%02x", Buf[i +2]); fprintf (Fileout,"%02x", Buf[i +1]); fprintf (Fileout,"%02x", Buf[i +0]); fprintf (Fileout,"; \ n"); Address++; } fprintf (Fileout,"[%d.. %d]: 0;\n", Address, maxaddr-1); fprintf (Fileout,"\n\nend;\n");                Fclose (fileout); //For Xilinx FPGA Coe fileFileout = fopen ("./xilinx.coe","W"); if(Fileout = =NULL) {printf ("Output File Create error!\n"); return 0; } fprintf (Fileout,"memory_initialization_radix=16;\nmemory_initialization_vector=\n", MAXADDR); Fseek (Filein,0L, Seek_set); Fread (buf, FileLen,1, Filein);  for(i =0; i < FileLen; i + =4) {fprintf (fileout,"%02x", Buf[i +3]); fprintf (Fileout,"%02x", Buf[i +2]); fprintf (Fileout,"%02x", Buf[i +1]); fprintf (Fileout,"%02x", Buf[i +0]); fprintf (Fileout,", \ n"); } fseek (Fileout,-2L, Seek_end); fprintf (Fileout,"; \ n");        Fclose (fileout); //Generic Data fileFileout = fopen ("./data.txt","W"); if(Fileout = =NULL) {printf ("Output File Create error!\n"); return 0; } Address=0x0; Fseek (Filein,0L, Seek_set); Fread (buf, FileLen,1, Filein);  for(i =0; i < FileLen; i + =4) {fprintf (fileout,"@%08x\n", address); fprintf (Fileout,"%02x", Buf[i +3]); fprintf (Fileout,"%02x", Buf[i +2]); fprintf (Fileout,"%02x", Buf[i +1]); fprintf (Fileout,"%02x", Buf[i +0]); fprintf (Fileout,"\ n"); Address++; }                 Free(BUF);        Fclose (Filein);    Fclose (fileout); }        return 0;}

Various soft core processor binary files FPGA initialization File Generator program