Verification of CRC-CCITT Based on OpenGL

Because I encountered many problems when designing the CRC module, I did not find an article with practical guidance on the Internet. After several simulation modifications and simulation, I got the correct result, therefore, we are willing to provide you with the entire design process in this article for you to quickly complete the design. This article mainly provides a set of feasible implementation methods for the actual application, and provides the design code and simulation results for your reference.

I. CRC Overview
CRC (cyclic redundancy check) is a common error check code used in digital communication. The feature is that the length of the information segment and validation field can be arbitrarily selected.
The verification method is to enable the sender to calculate the binary division of the divisor for information data, attach the obtained remainder to the end of the frame, and send it to the receiver. The receiver also implements a similar algorithm, the remainder of the comparison results on both sides. If the result is the same, the received information is complete and correct to ensure the correctness and integrity of data transmission.
Specifically, after the K-bit information code is combined with the R-bit verification code, the entire encoding length is n (= K + r) bits. Therefore, this encoding is also called (n, k) code. For a given (n, k) code, it can be proved that there is a polynomial g (x) whose maximum power is N-K = R ). The checksum code for K-bit information can be generated based on g (x), while G (x) is called the polynomial of CRC code generation.
The specific generation process of the Verification Code is as follows: assume that the information to be sent is represented by polynomial C (x), and C (X) is shifted to the r bit (which can be expressed as C (X)So that the right side of C (X) is null out of the r bit, which is the position of the verification code. Use C (X)The remainder obtained by dividing 2r by the generated polynomial g (x) is the verification code FCS (frame check series ).
Any code composed of binary strings can correspond to a polynomial with a coefficient of only '0' and a value of '1. For example, code 1010111 corresponds to a polynomial of X6 + X4 + X2 + x + 1, while a polynomial of code 101111 corresponds to X5 + X3 + X2 + x + 1.
CRC verification is divided into many different standards based on the generated polynomials used. Common include:
Example of name generation Polynomial

CRC-4 X4 + x + 1 3 ITU g.704

CRC-8 X8 + X5 + X4 + 1 31 DS18B20
CRC-12 X12 + X11 + X3 + X2 + x + 1 0x80f
CRC-16 x16 + x15 + X2 + 1 0x8005 IBM SDLC
CRC-ITU (CCITT) x16 + X12 + X5 + 1 0X1021 ISO HDLc, ITU
CRC-32 x32 + X26 + x23 +... + X2 + x + 1 0x04c11db7 zip, rar
CRC-32c x32 + x28 + x27 +... + X8 + X6 + 1 0x1edc6f41 sctp
Note: The maximum bit of the simple expression should be 1, which is omitted here;

II. Implementation Method
The standard described in this article is CRC-ITU (CCITT-XMODEM), that is, the generated polynomial is 0X1021
0X1021 = 0x11021 = 0001

An online CRC verification website is provided to facilitate verification.
Https://www.lammertbies.nl/comm/info/crc-calculation.html

The source code is generated on the source code website as needed, and then modified according to your needs for simulation verification;
The steps for generating Source Code are as follows:
Step 1: http://outputlogic.com /? Page_id = 321
Step 2: select the input data Bit Width and output verification code Bit Width based on actual requirements. The CRC verification standard is customized or optional;

Step 3: If user defined is selected, select the User-Defined polynomial on the second page. In this simulation, The CCITT standard is used, that is, the generated polynomial is x16 + X12 + X5 + 1, select 1, X5, and X12, because x16 is the default value;

Step 4: Modify the generated code in the language of OpenGL or VHDL and apply it to the actual situation;

3. Practical Application Simulation
A specific CRC verification design and simulation are conducted based on the actual application scenarios of the author. The CRC verification calculation process in the always module does not need to be understood. If necessary, you can download the article provided by this website (the download code will be attached)
A Practical parallel CRC generation method
Common CRC verification methods include Binary Division calculation and Table query. For detailed calculation principles, see the following link:
78693781
The Code is as follows:

Module CRC (
Input CLK, // input clock
Input reset, // overall reset signal
Input crc_en, // select whether to perform the next CRC operation
Input [63: 0] data_in, // the input data is 64-bit
Output [] crc_out // the output data indicates that the CRC verification result is 16 bits.
);
Reg [15:0] lfsr_q, lfsr_c;
Wire reset;
Assign crc_out = lfsr_c;

Always @ (*) begin
Lfsr_c [0] = lfsr_q [0] ^ lfsr_q [1] ^ lfsr_q [3] ^ lfsr_q [4] ^ lfsr_q [7] ^ lfsr_q [8] ^ lfsr_q [10] ^ lfsr_q [15] ^ data_in [0] ^ data_in [4] ^ data_in [8] ^ data_in [11] ^ data_in [12] ^ data_in [19] ^ data_in [20] ^ data_in [22] ^ data_in [26] ^ data_in [27] ^ data_in [28] ^ data_in [32] ^ data_in [33] ^ data_in [35] ^ data_in [42] ^ data_in [48] ^ data_in [49] ^ data_in [51] ^ data_in [52] ^ data_in [55] ^ data_in [56] ^ data_in [58] ^ data_in [63];
Lfsr_c [1] = lfsr_q [1] ^ lfsr_q [2] ^ lfsr_q [4] ^ lfsr_q [5] ^ lfsr_q [8] ^ lfsr_q [9] ^ lfsr_q [11] ^ data_in [1] ^ data_in [5] ^ data_in [9] ^ data_in [12] ^ data_in [13] ^ data_in [20] ^ data_in [21] ^ data_in [23] ^ data_in [27] ^ data_in [28] ^ data_in [29] ^ data_in [33] ^ data_in [34] ^ data_in [36] ^ data_in [43] ^ data_in [49] ^ data_in [50] ^ data_in [52] ^ data_in [53] ^ data_in [56] ^ data_in [57] ^ data_in [59];
Lfsr_c [2] = lfsr_q [2] ^ lfsr_q [3] ^ lfsr_q [5] ^ lfsr_q [6] ^ lfsr_q [9] ^ lfsr_q [10] ^ lfsr_q [12] ^ data_in [2] ^ data_in [6] ^ data_in [10] ^ data_in [13] ^ data_in [14] ^ data_in [21] ^ data_in [22] ^ data_in [24] ^ data_in [28] ^ data_in [29] ^ data_in [30] ^ data_in [34] ^ data_in [35] ^ data_in [37] ^ data_in [44] ^ data_in [50] ^ data_in [51] ^ data_in [53] ^ data_in [54] ^ data_in [57] ^ data_in [58] ^ data_in [60];
Lfsr_c [3] = lfsr_q [3] ^ lfsr_q [4] ^ lfsr_q [6] ^ lfsr_q [7] ^ lfsr_q [10] ^ lfsr_q [11] ^ lfsr_q [13] ^ data_in [3] ^ data_in [7] ^ data_in [11] ^ data_in [14] ^ data_in [15] ^ data_in [22] ^ data_in [23] ^ data_in [25] ^ data_in [29] ^ data_in [30] ^ data_in [31] ^ data_in [35] ^ data_in [36] ^ data_in [38] ^ data_in [45] ^ data_in [51] ^ data_in [52] ^ data_in [54] ^ data_in [55] ^ data_in [58] ^ data_in [59] ^ data_in [61];
Lfsr_c [4] = lfsr_q [4] ^ lfsr_q [5] ^ lfsr_q [7] ^ lfsr_q [8] ^ lfsr_q [11] ^ lfsr_q [12] ^ lfsr_q [14] ^ data_in [4] ^ data_in [8] ^ data_in [12] ^ data_in [15] ^ data_in [16] ^ data_in [23] ^ data_in [24] ^ data_in [26] ^ data_in [30] ^ data_in [31] ^ data_in [32] ^ data_in [36] ^ data_in [37] ^ data_in [39] ^ data_in [46] ^ data_in [52] ^ data_in [53] ^ data_in [55] ^ data_in [56] ^ data_in [59] ^ data_in [60] ^ data_in [62];
Lfsr_c [5] = lfsr_q [0] ^ lfsr_q [1] ^ lfsr_q [3] ^ lfsr_q [4] ^ lfsr_q [5] ^ lfsr_q [6] ^ lfsr_q [7] ^ lfsr_q [9] ^ lfsr_q [10] ^ lfsr_q [12] ^ lfsr_q [13] ^ data_in [0] ^ data_in [4] ^ data_in [5] ^ data_in [8] ^ data_in [9] ^ data_in [11] ^ data_in [12] ^ data_in [13] ^ data_in [16] ^ data_in [17] ^ data_in [19] ^ data_in [20] ^ data_in [22] ^ data_in [24] ^ data_in [25] ^ data_in [26] ^ data_in [28] ^ data_in [31] ^ data_in [35] ^ data_in [37] ^ data_in [38] ^ data_in [40] ^ data_in [42] ^ data_in [47] ^ data_in [48] ^ data_in [49] ^ data_in [51] ^ data_in [52] ^ data_in [53] ^ data_in [54] ^ data_in [55] ^ data_in [57] ^ data_in [58] ^ data_in [60] ^ data_in [61];
Lfsr_c [6] = lfsr_q [0] ^ lfsr_q [1] ^ lfsr_q [2] ^ lfsr_q [4] ^ lfsr_q [5] ^ lfsr_q [6] ^ lfsr_q [7] ^ lfsr_q [8] ^ lfsr_q [10] ^ lfsr_q [11] ^ lfsr_q [13] ^ lfsr_q [14] ^ data_in [1] ^ data_in [5] ^ data_in [6] ^ data_in [9] ^ data_in [10] ^ data_in [12] ^ data_in [13] ^ data_in [14] ^ data_in [17] ^ data_in [18] ^ data_in [20] ^ data_in [21] ^ data_in [23] ^ data_in [25] ^ data_in [26] ^ data_in [27] ^ data_in [29] ^ data_in [32] ^ data_in [36] ^ data_in [38] ^ data_in [39] ^ data_in [41] ^ data_in [43] ^ data_in [48] ^ data_in [49] ^ data_in [50] ^ data_in [52] ^ data_in [53] ^ data_in [54] ^ data_in [55] ^ data_in [56] ^ data_in [58] ^ data_in [59] ^ data_in [61] ^ data_in [62];
Lfsr_c [7] = lfsr_q [1] ^ lfsr_q [2] ^ lfsr_q [3] ^ lfsr_q [5] ^ lfsr_q [6] ^ lfsr_q [7] ^ lfsr_q [8] ^ lfsr_q [9] ^ lfsr_q [11] ^ lfsr_q [12] ^ lfsr_q [14] ^ lfsr_q [15] ^ data_in [2] ^ data_in [6] ^ data_in [7] ^ data_in [10] ^ data_in [11] ^ data_in [13] ^ data_in [14] ^ data_in [15] ^ data_in [18] ^ data_in [19] ^ data_in [21] ^ data_in [22] ^ data_in [24] ^ data_in [26] ^ data_in [27] ^ data_in [28] ^ data_in [30] ^ data_in [33] ^ data_in [37] ^ data_in [39] ^ data_in [40] ^ data_in [42] ^ data_in [44] ^ data_in [49] ^ data_in [50] ^ data_in [51] ^ data_in [53] ^ data_in [54] ^ data_in [55] ^ data_in [56] ^ data_in [57] ^ data_in [59] ^ data_in [60] ^ data_in [62] ^ data_in [63];
Lfsr_c [8] = lfsr_q [2] ^ lfsr_q [3] ^ lfsr_q [4] ^ lfsr_q [6] ^ lfsr_q [7] ^ lfsr_q [8] ^ lfsr_q [9] ^ lfsr_q [10] ^ lfsr_q [12] ^ lfsr_q [13] ^ lfsr_q [15] ^ data_in [3] ^ data_in [7] ^ data_in [8] ^ data_in [11] ^ data_in [12] ^ data_in [14] ^ data_in [15] ^ data_in [16] ^ data_in [19] ^ data_in [20] ^ data_in [22] ^ data_in [23] ^ data_in [25] ^ data_in [27] ^ data_in [28] ^ data_in [29] ^ data_in [31] ^ data_in [34] ^ data_in [38] ^ data_in [40] ^ data_in [41] ^ data_in [43] ^ data_in [45] ^ data_in [50] ^ data_in [51] ^ data_in [52] ^ data_in [54] ^ data_in [55] ^ data_in [56] ^ data_in [57] ^ data_in [58] ^ data_in [60] ^ data_in [61] ^ data_in [63];
Lfsr_c [9] = lfsr_q [3] ^ lfsr_q [4] ^ lfsr_q [5] ^ lfsr_q [7] ^ lfsr_q [8] ^ lfsr_q [9] ^ lfsr_q [10] ^ lfsr_q [11] ^ lfsr_q [13] ^ lfsr_q [14] ^ data_in [4] ^ data_in [8] ^ data_in [9] ^ data_in [12] ^ data_in [13] ^ data_in [15] ^ data_in [16] ^ data_in [17] ^ data_in [20] ^ data_in [21] ^ data_in [23] ^ data_in [24] ^ data_in [26] ^ data_in [28] ^ data_in [29] ^ data_in [30] ^ data_in [32] ^ data_in [35] ^ data_in [39] ^ data_in [41] ^ data_in [42] ^ data_in [44] ^ data_in [46] ^ data_in [51] ^ data_in [52] ^ data_in [53] ^ data_in [55] ^ data_in [56] ^ data_in [57] ^ data_in [58] ^ data_in [59] ^ data_in [61] ^ data_in [62];
Lfsr_c [10] = lfsr_q [4] ^ lfsr_q [5] ^ lfsr_q [6] ^ lfsr_q [8] ^ lfsr_q [9] ^ lfsr_q [10] ^ lfsr_q [11] ^ lfsr_q [12] ^ lfsr_q [14] ^ lfsr_q [15] ^ data_in [5] ^ data_in [9] ^ data_in [10] ^ data_in [13] ^ data_in [14] ^ data_in [16] ^ data_in [17] ^ data_in [18] ^ data_in [21] ^ data_in [22] ^ data_in [24] ^ data_in [25] ^ data_in [27] ^ data_in [29] ^ data_in [30] ^ data_in [31] ^ data_in [33] ^ data_in [36] ^ data_in [40] ^ data_in [42] ^ data_in [43] ^ data_in [45] ^ data_in [47] ^ data_in [52] ^ data_in [53] ^ data_in [54] ^ data_in [56] ^ data_in [57] ^ data_in [58] ^ data_in [59] ^ data_in [60] ^ data_in [62] ^ data_in [63];
Lfsr_c [11] = lfsr_q [0] ^ lfsr_q [5] ^ lfsr_q [6] ^ lfsr_q [7] ^ lfsr_q [9] ^ lfsr_q [10] ^ lfsr_q [11] ^ lfsr_q [12] ^ lfsr_q [13] ^ lfsr_q [15] ^ data_in [6] ^ data_in [10] ^ data_in [11] ^ data_in [14] ^ data_in [15] ^ data_in [17] ^ data_in [18] ^ data_in [19] ^ data_in [22] ^ data_in [23] ^ data_in [25] ^ data_in [26] ^ data_in [28] ^ data_in [30] ^ data_in [31] ^ data_in [32] ^ data_in [34] ^ data_in [37] ^ data_in [41] ^ data_in [43] ^ data_in [44] ^ data_in [46] ^ data_in [48] ^ data_in [53] ^ data_in [54] ^ data_in [55] ^ data_in [57] ^ data_in [58] ^ data_in [59] ^ data_in [60] ^ data_in [61] ^ data_in [63];
Lfsr_c [12] = lfsr_q [0] ^ lfsr_q [3] ^ lfsr_q [4] ^ lfsr_q [6] ^ lfsr_q [11] ^ lfsr_q [12] ^ lfsr_q [13] ^ lfsr_q [14] ^ lfsr_q [15] ^ data_in [0] ^ data_in [4] ^ data_in [7] ^ data_in [8] ^ data_in [15] ^ data_in [16] ^ data_in [18] ^ data_in [22] ^ data_in [23] ^ data_in [24] ^ data_in [28] ^ data_in [29] ^ data_in [31] ^ data_in [38] ^ data_in [44] ^ data_in [45] ^ data_in [47] ^ data_in [48] ^ data_in [51] ^ data_in [52] ^ data_in [54] ^ data_in [59] ^ data_in [60] ^ data_in [61] ^ data_in [62] ^ data_in [63];
Lfsr_c [13] = lfsr_q [0] ^ lfsr_q [1] ^ lfsr_q [4] ^ lfsr_q [5] ^ lfsr_q [7] ^ lfsr_q [12] ^ lfsr_q [13] ^ lfsr_q [14] ^ lfsr_q [15] ^ data_in [1] ^ data_in [5] ^ data_in [8] ^ data_in [9] ^ data_in [16] ^ data_in [17] ^ data_in [19] ^ data_in [23] ^ data_in [24] ^ data_in [25] ^ data_in [29] ^ data_in [30] ^ data_in [32] ^ data_in [39] ^ data_in [45] ^ data_in [46] ^ data_in [48] ^ data_in [49] ^ data_in [52] ^ data_in [53] ^ data_in [55] ^ data_in [60] ^ data_in [61] ^ data_in [62] ^ data_in [63];
Lfsr_c [14] = lfsr_q [1] ^ lfsr_q [2] ^ lfsr_q [5] ^ lfsr_q [6] ^ lfsr_q [8] ^ lfsr_q [13] ^ lfsr_q [14] ^ lfsr_q [15] ^ data_in [2] ^ data_in [6] ^ data_in [9] ^ data_in [10] ^ data_in [17] ^ data_in [18] ^ data_in [20] ^ data_in [24] ^ data_in [25] ^ data_in [26] ^ data_in [30] ^ data_in [31] ^ data_in [33] ^ data_in [40] ^ data_in [46] ^ data_in [47] ^ data_in [49] ^ data_in [50] ^ data_in [53] ^ data_in [54] ^ data_in [56] ^ data_in [61] ^ data_in [62] ^ data_in [63];
Lfsr_c [15] = lfsr_q [0] ^ lfsr_q [2] ^ lfsr_q [3] ^ lfsr_q [6] ^ lfsr_q [7] ^ lfsr_q [9] ^ lfsr_q [14] ^ lfsr_q [15] ^ data_in [3] ^ data_in [7] ^ data_in [10] ^ data_in [11] ^ data_in [18] ^ data_in [19] ^ data_in [21] ^ data_in [25] ^ data_in [26] ^ data_in [27] ^ data_in [31] ^ data_in [32] ^ data_in [34] ^ data_in [41] ^ data_in [47] ^ data_in [48] ^ data_in [50] ^ data_in [51] ^ data_in [54] ^ data_in [55] ^ data_in [57] ^ data_in [62] ^ data_in [63];
End
// This code segment is a specific CRC calculation process, based on lfsr (Linear Feedback Shift Register );

Always @ (posedge CLK, negedge reset) begin
If (! Reset) begin
Lfsr_q <= {16 {1 'b0}; // The initial value of ccitt_xmodem is 16'h0; other protocols can be modified as needed;
End
Else begin
Lfsr_q <= crc_en? Lfsr_c: lfsr_q; // here, the crc_en is set to 0, and the CRC verification result is only calculated once. Otherwise, the Operation will continue.
End
End
Endmodule

Compile the testbench file to simulate this module:

Module crc_simul;
Reg [63: 0] data_in;
Reg crc_en;
Reg reset;
Reg CLK;
Wire [15:0] crc_out;
Crc uut (
. Data_in (data_in ),
. Crc_en (crc_en ),
. Crc_out (crc_out ),
. Reset (reset ),
. CLK (CLK)
);
Initial begin
Data_in = 64'd0;
Crc_en = 1' B0;
Reset = 1' B0;
CLK = 1' B0;
#9;
Reset = 1 'b1;
#200;
Data_in = {8 'hff, 8' HFF, 8' Haa, 8' h55, 8' H00, 8' h01, 16' h13ec}; // The result should be 3dc3;
#500;
Data_in = {8 'hff, 8' HFF, 8' Haa, 8'h55, 8' H00, 8' h01, 16' h01f4}; // The result is cbeb;
End

Always #1 CLK = ~ CLK;
Endmodule

The simulation results are as follows:

It can be verified that the simulation results are correct and can also be run correctly in practical applications;

Verification of CRC-CCITT Based on OpenGL