Verilog Basic Knowledge 7 (FIFO depth calculation)

Requirement Description: Verilog design

Content: First part FIFO depth discussion

Second part FIFO depth calculation

From: The time of the poem

first part FIFO in depth discussion

Original: http://comm.chinaaet.com/adi/blogdetail/37555.html

actually very ashamed, before this use FIFO are directly with the IP, because the application scenario is very simple, so the FIFO depth of choice is more casual, and did not think a lot. Today on the Internet to see an asynchronous FIFO depth calculation of the topic, found that this piece is not familiar with, so pay attention to below, write some of their own understanding it. Explained in advance, because I actually did not encounter the need to calculate the FIFO depth of the scene, so there may be some understanding is wrong, I hope you can criticize the hero.

first of all, we must understand the FIFO application scenario, this will directly affect the FIFO depth calculation, if the interviewer throws the problem, then there is unclear where, should be asked. If it is a written examination or the need to calculate the FIFO depth in the project, then you need to consider clearly.

second, asynchronous FIFO, read-write clock different frequency, then FIFO is mainly used for data caching, we choose the FIFO depth should be able to ensure that in the most extreme cases, still do not overflow. Therefore, the premise is generally that the write clock frequency is greater than the read clock frequency, but if the write operation is continuous data flow, then the large FIFO can not guarantee that the data does not overflow. Therefore, it can be considered that the transmission of the write data is "burst burst", that is, the write operation is not continuous, the designer needs to control or control the write operation according to the full flag.

macroscopic, from the whole time domain, "write data = Read Data", this condition must be satisfied, if this large condition is not satisfied, with FIFO is no effect. However, in the sender "burst" to send data within the time t, is very likely to write data > read data, so the depth of the FIFO to be able to ensure that, in this time t, if the receiver failed to send the sender of the data received, the rest of the data can be stored in the FIFO and will not overflow, In the "Idle time slot" where the sender stops sending data, the receiver can easily receive the remaining data.

The Scarlet Letter part is the most important part in the FIFO depth calculation. Then look at an example, this is I read a netizen write, is he met a pen question.

a 8bit wide afifo with an input clock of 100MHz, an output clock of 95MHz, a package of 4Kbit, and a large enough transmit space between two package. Ask the depth of Afifo.

because the netizen may be just a brief, so the information is not complete, my personal understanding is such a scenario, an asynchronous FIFO, read and write frequency, read and write bit width is the same. Send a burst burst of data is 4Kbit, that is 500Word, there is enough time between the two burst bursts, so we only consider the sender burst send data in the time t, if the receiving party can not fully accept the data, the rest of the data may exist in the FIFO and do not overflow , the receiver can read the data from the FIFO within the time period when the sender stops burst sending the data. First the sender burst the time period for sending the data is T = 500/100mhz, the amount of data sent is B_send = 500word, while in T this time, the receiver can accept the amount of data is B_rec = T*95mhz = $ * 95/100 Word = 475word, so b_remain = B_send-b_rec = 500-475 = 25. Then the FIFO depth must be at least 25 or greater.

look at another example, or find it on the Internet,

Write clock frequency w_clk,
Read Clock frequency R_CLK,
Write clock cycle, each B clock cycle will have a data write FIFO
Read clock cycle, x data readout FIFO per y clock cycle
Then, what is the minimum depth of FIFO?

First, we can assume that the write operation is burst burst.

Second, the efficiency of the write operation is not 100%, but A/b, so we can consider the actual F_WR = (A/b) *W_CLK, the same, the actual F_RD = (x/y) *r_clk.

In addition, unlike the first example, this topic does not constrain the burst burst scene, under normal circumstances, it should be

Idle---burst burst---idle---burst burst---idle---burst burst. But in our calculations, we need to consider the most extreme cases,

Idle---burst burst---burst burst---idle---burst burst---idle. That is, in the transmission process, there may be "back to back" situation, then we design the FIFO depth must be guaranteed, in the "back to back" time period, if the receiver cannot accept all the data, then the remaining data can be stored in the FIFO and will not overflow. Then you can start the calculation. Assuming "back-to-back" when the data is sent = BL, then "back to back" time = BL/W_CLK, note that this period of time F_WR = W_CLK instead of the previously mentioned

(A/b) *w_clk. During this period, the receiver can accept the data = (BL/W_CLK) * (x/y) *R_CLK,
The remaining amount of data = BL-(BL/W_CLK) * (x/y) *R_CLK, then the FIFO depth must be at least
"Depth = BL-(BL/W_CLK) * (x/y) *r_clk" such depth.
Transform the above formula to get depth = BL-BL * (x/y) * (R_CLK/W_CLK). This formula is the formula for calculating FIFO depth on the Internet, which I think is the reasoning process.

One premise of the above discussion is that the FIFO read-write bit width is consistent, if this condition is not satisfied, then the depth of the FIFO calculation is more complicated, but we can still be the FIFO read and write bit width is also folded into a certain factor, into the actual F_WR = (A/b) *W_CLK and F_RD = (x/y) *R_CLK, should be able to solve.

second part FIFO depth calculation

Original http://blog.sina.com.cn/s/blog_6a89f7010100mnua.html

If the data flow is continuous, the FIFO depth no matter how much, as long as the read-write clock is not homologous with the same frequency will be lost;
FIFO is used to buffer block data flow, generally used in write fast reading slow,
FIFO depth/(write rate-readout rate) = FIFO fill time should be greater than packet delivery time = data Volume/write rate

Example: A/D sampling rate 50MHZ,DSP read A/d read the rate of 40MHz, or the loss of 100,000 sampling data into the DSP, in A/d in and DSP at least a large capacity (depth) of the FIFO line?
100,000/50mhz = 1/500 s = 2ms
(50mhz-40mhz) * 1/500 = 20k is both FIFO depth.

A wrong algorithm (I also made the same mistake):
100,000/40mhz= 1/400s = 2.50ms
(50m-400m) *1/400 =25k. Then the data entered is not 100K, but 100k+50m* (0.0025-0.002) =125,000bit, error in the calculation of the time
Asynchronous FIFO Design Considerations

The design of asynchronous FIFO is very different from the design of synchronous FIFO, and the problem of cross-clock domain processing should be considered when designing.
1, FIFO design must solve the problem of empty and full control;
2, asynchronous FIFO can consider the write addr in the write clock domain into gray code, and then through the reading clock to register, converted to the reading clock domain, to solve the empty mark signal;
3, asynchronous FIFO can consider the read addr in the reading clock domain converted to gray code, and then through the write clock to register, converted to the write clock domain, to solve the full mark signal;
4, the use of gray code in gray code can be the addr value of continuous changes in the Regulation (but addr will have multiple bit jumps) into the gray code only 1 bit jump, so in the cross-clock domain transfer will not occur when there is a large difference in asynchronous (asynchronous clock sampling will occur metastable phenomenon) , up to the original addr value plus 1 or minus 1, which will not cause the FIFO state error;

When the FIFO size is very large. Using gray code becomes less advantageous.
Because you want to change from binary to gray and back again.

At this point, the asynchronous handshake will be used to move the address to another
Inside the clock domain. Simply say with a request and an ACK.
I haven't done it specifically.

But this is a question that almost every American company has to ask.
So it's good to study a little.

Calculate FIFO Depth-translation-English-Chinese version
Introduction
One of the most common questions in interviews is what to calculate the depth of a FIFO.
One of the most frequently asked questions in the trial process is how to calculate the depth of a FIFO.

Fifo is used as buffering element or queueing element in the system, which are by common sense are required only if you SL ow at reading than the write operation.
FIFO is used as a buffer or queue in the system, usually when the read rate is slower than the write rate, a FIFO is required.

So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is Written and the data rate at which data is read.
So the depth of FIFO depends on the amount of data that needs to be buffered, and the amount of buffered data depends on the write rate and read rate.

Statistically, Data rate varies in the system majorily depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under Consi Deration.
Statistics show that the change of data rate in the system is mainly dependent on the load of the system. So, in order to get a secure FIFO, at design time, we need to consider the worst case of data transfer through FIFO.

For worst case scenario, difference between the data rate between write and read should is maximum. Hence, for write operation maximum data rate should is considered and for read operation minimum data rate should be Consi dered.
In the worst case, the rate difference between read and write data should be the maximum value. In other words, the write operation rate should take the maximum write rate, while the read operation should pick a small read rate.

So in the question itself, data rate of read operation was specified by T He number of idle cycles and for write operation, maximum data rate should is considered with no idle cycle.
As the problem itself, the data rate of the read operation is determined by the idle period, and for the write operation, the maximum write data rate should not take into account the idle period.

For the so-write operation, we need to know data rate = number of the data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the Writing side data rat E and its own reading-which is frd/idle_cycle_rd.
Thus, for the read operation, we have data rate = number of data * rate of clock. The written party is the data inflow, and the reading is the data exposed side. The rate of read-side depends on the rate of the writing party and its own read rate (FRD/IDLE_CYCLE_RD.)

In order to know the data rate of write operation, we need to know number of data in a Burst which we had assumed to be B .
In order to know the write-side data rate, we need to be aware of the amount of data in burst mode, and we assume that it is B.

So following up with the equation as explained below:fifo size = size T o Be buffered = B-b * Frd/(fwr* idle_cycle _rd). The
refers to the following equation: Fifo size = size to be buffered = B-b * Frd/(fwr* idle_cycle _rd).
Here we had not considered the sychnronizing latency if Write and Read clocks is asynchronous. Greater The Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.
Here, we do not consider the delay that is introduced due to asynchronous read and write needs synchronization. The larger the delay, the greater the FIFO is required to buffer more and write the data.

Example:fifo Depth Calculation
Example: Calculating FIFO depth
Assume that we had to design a FIFO with following requirements and we want to calculate minumum FIFO depth,
Impurities we need to design the FIFO for the requirements below, we need to calculate its minimum depth.

A synchronized FIFO xor FIFO
Writing Clock 30mhz-f1 Write clocks
Reading Clock 40mhz-f2 reading clocks
Writing Burst size-b Burst Data volume
Case 1:there are 1 idle clock cycle for reading Side-i read square one idle cycle
Case 2:there is ten idle clock cycle for reading Side-i read Square 10 idle cycles
FIFO depth calculation = B-b *f2/(f1*i)

If if we have alternate read cycles i.e between, the read cycle there is IDLE cycle.
If we have changed the read cycle, for example, there is an idle period in two read cycles.

FIFO depth calculation = B-b * f2/(f1*2)
In our present problem FIFO depth = B-b *40/(30*2)
= B (1-2/3) = B/3
That means if we Burst amount of data is ten, fifodepth = 10/3 = 3.333 = 4 (approximatly)
If B = FIFO depth = 20/3 = 6.6 = 7or 8 (clocks is asynchronous)
If B = Depth FIFO = 30/3 = 10+1 = One (clocks is asynchronous)
If Ten IDLE cycles betweeen the read cycles.
FIFO DEPTH = B-b *f2/(f1*10). = B (1-4/30) = b * 26/30

Verilog Basic Knowledge 7 (FIFO depth calculation)