Verilog Disable usage (easy to mistake!) ）

The Disable statement can exit any loop and be able to terminate any begin. The execution of the end block is used in simulation validation. For examplebegin: One for(i=1;i<5; i=i+1)begin: Bothif(a==0)DisableOne//from one this begin. End, terminating the forif(a==1)Disableboth;//from the beginning of this. Out of the end block, jumping out of the loopEndEndSee the following example on the Internet, one meaning:begin: BreakForeverbegin: Continue ...DisableContinue;//continue next Iteration ...Disablebreak;//Exit Forever Loop...End //continue toEnd //Terminate

Verilog Disable usage (easy to mistake!) ）