Verilog HDL--VGA Display

ModuleVGA (Clk,rst_n, Hsync,vsync, vga_r,vga_g,vga_b);inputClk//50MHzinputRst_n;//low-Power resetOutputHSync//Line Sync SignalOutputVSync//Field Sync SignalOutputVga_r;OutputVga_g;OutputVga_b;//--------------------------------------------------Reg[Ten:0] x_cnt;//Line coordinatesReg[9:0] y_cnt;//Column coordinates always@ (PosedgeClassor Negedgerst_n)if(!rst_n) x_cnt <= One'D0;    Else if(x_cnt = = One'd1039) x_cnt <='D0; Elsex_cnt <= x_cnt+1'B1; always@ (PosedgeClassor Negedgerst_n)if(!rst_n) y_cnt <=Ten'D0;    Else if(y_cnt = =Ten'd665) y_cnt <='D0; Else if(x_cnt = = One'd1039) y_cnt <= y_cnt+1'B1;//-------------------------------------------------- WireValid//Valid display area flagAssignValid = (x_cnt >= One'd187) && (x_cnt < one'd987)&& (y_cnt >=Ten'd31) && (y_cnt <'d631);  Wire[9:0] Xpos,ypos;//valid display area coordinatesAssignXpos = x_cnt- One'd187;AssignYpos = y_cnt-Ten'D31;//--------------------------------------------------RegHsync_r,vsync_r;//Synchronous Signal Generation always@ (PosedgeClassor Negedgerst_n)if(!rst_n) Hsync_r <=1'B1;    Else if(x_cnt = = One'd0) hsync_r <= 1'B0;//Generate HSync Signal    Else if(x_cnt = = One'd120) hsync_r <= 1'B1; always@ (PosedgeClassor Negedgerst_n)if(!rst_n) Vsync_r <=1'B1;    Else if(y_cnt = =Ten'd0) vsync_r <= 1'B0;//Generate VSync Signal    Else if(y_cnt = =Ten'd6) vsync_r <= 1'B1;AssignHSync =Hsync_r;AssignVSync =Vsync_r;//--------------------------------------------------    //Display a rectangular box WireA_dis,b_dis,c_dis,d_dis;//rectangular box display area positioningAssignA_dis = ((xpos>= $) && (xpos<= -) )                 && (ypos>= $) && (ypos<=460) ); AssignB_dis = ((xpos>=580) && (xpos<= -) )                && (ypos>= $) && (ypos<=460) );AssignC_dis = ((xpos>= -) && (xpos<=580) )                 && (ypos> $) && (ypos<= the) ); AssignD_dis = ((xpos>= -) && (xpos<=580) )                && (ypos>= the) && (ypos<=460) ); //show a small rectangle WireE_rdy;//rectangular display of valid rectangular areasAssignE_rdy = ((xpos>=385) && (xpos<=415) )                && (ypos>=285) && (ypos<=315) );//--------------------------------------------------     //r,g,b Control LCD color display, background display blue, rectangular box shows red and blueAssignVga_r = valid? E_rdy:1'B0;AssignVga_g = valid? (A_dis | b_dis | c_dis | d_dis):1'B0;AssignVga_b = valid? ~ (A_dis | b_dis | c_dis | d_dis):1'B0; Endmodule

Verilog HDL--VGA Display