Verilog if (0) if (1) Tips

This article mainly introduces Verilog if (0), if (1) to Verilog syntax correction function.

Verilog syntax is too simple, has always been our criticism of the place, want to achieve a function sometimes you have to knock on a large section of the function of repeated code snippets, sometimes just one of the parameters change. This time lazy we will come up with a solution, fortunately in the Verilog Standard (1995,2001) standard has a macro support. As we all know, the role of macros is to generate code, with the help of macros we can put a lot of repetitive functions into the macro, and then write a macro directly in the program. The benefit of this is that it has no effect on our overall code and the results of the synthesis, because the macro is expanded at compile time.

OK to use the macro has freed us a little work. I modeled a scenario like the one below.

Always @ (Posedge CLK) begin case (counter) [D1:begin ANSWER=1/3; Signal=0;signal=1;end ' D2:begin ANSWER=2/3; Signal=0;signal=1;end ' D3:begin ANSWER=3/3;        Signal=0;signal=1;end ... + ' D16:begin answer=16/3;signal=0;signal=1;end endcase End

Do not think about the function of this example, this is not our focus, I want to create is each case contains multiple sentences, but each case has a regular difference of a scene.

Well, what about the code above, and if you've been in touch with other languages, then you're going to have a bad time with that, (well, I admit I don't like it).

Next we use our powerful helper macro brother to help us reduce the workload.

Always @ (Posedge CLK) begincase (counter) + ' D1: ' div (1) + ' D2: ' div (2) + ' D3: ' div (3) ... + ' D15: ' Div (endcaseend)

The macro is defined as

' Define DIV (x) begin signal=0; ANSWER=X/3; signal=1; End

A very simple parameter macro.

But is it really satisfying to see the use of the macro above?  Where's the semicolon for the DIV (1)? Someone will tell me that Verilog Rihon is a simple alternative, if you add a semicolon after the div (x), then the expansion will be

Begin Signal=0;answer=x/3;signal=1;end;

The end, followed by the semicolon syntax is not correct, so the role of this article will come out, this article is to such a macro can not be added to the syntax correction. Someone's going to spit. I said as to this, why, just as I started to see C language do{...} while (0). If you don't understand why you're doing this, just search for the background. Do while (0).

Using the IF (1), if (0) syntax correction after the macro is as follows

' Define DIV (x) if (1) begin signal=0; ANSWER=X/3; signal=1; End  Else if (0)

In this way, we use the code to become

Always @ (Posedge CLK) begincase (counter) + ' D1: ' div (1); + ' D2: ' div (2); + ' D3: ' div (3); + ' D16: ' div (+); endcaseend

This is in line with the general syntax. Interestingly, when I looked at its macro expansion with IVERILOG-E, I found that when I unfolded it, I removed the IF (1), if (0), so our revised macro did not have a trace effect on the circuit, just to facilitate our human writing habits, as well as reading habits.

Verilog if (0) if (1) Tips