Verilog implementation FIFO (reprint)

For the FIFO based on the monomer memory, as a data buffer, the data storage structure and RAM are consistent, but the access method is different. Because each storage unit in RAM can be read and write randomly, the FIFO's first position and queue length can be floating. To do this, two address registers are used to store the read address (that is, the first element address of the team) and the write address (that is, the end-of-line element address plus 1). The information stored in the FIFO is not moved during the read and write process, but is indicated by changing the read address or writing address to indicate the first team's tail.
The design of the 32x8 FIFO adopts the alternating reading and writing mechanism of the dual-body memory, so that the other memory can be read while one memory is written, while the other memory can be written by one of the memory read operations. High-speed data buffering is achieved at a rate higher than the FIFO of the monomer memory.

The generation of the

1 pointer and the full empty signal
      empty/Full flag is the core of the FIFO. How to correctly design this part of the logic, directly affect the performance of the FIFO.
      for a synchronous FIFO, the read-write pointer points to the initial position of the memory, and each time a read and write operation is performed, the corresponding pointer increments once, pointing to the next memory location. When the pointer moves to the last position in memory, it jumps back to its original position. In the case of non-full or non-empty FIFO, this process will continue as the read-write control signal changes. If the FIFO is in an empty state, the next read action will result in a downward overflow (underflow), an invalid data being read out, and a write action for a full FIFO will cause an upward overflow (overflow) and a useful data to be overwritten with the newly written data. Both cases belong to the misoperation, so it is necessary to set the full and empty two signals, the full signal setting indicates that the FIFO is full state, the full signal reset indicates that the FIFO is not full, there is space to write data, the null signal position indicates that the FIFO is empty, the null signal reset means that the FIFO is not empty, There are valid data that can be read out. The FIFO may be in full or empty state when the reading pointer and the write pointer are equal and point to the same memory location. It is possible to determine or differentiate whether a FIFO is in full state or empty state by different methods, that is, whether the write pointer catches the reading pointer from the back, or the read pointer catches the write pointer from behind.
      The method used in this article is to expand the read and write address registers by one bit, set the highest bit to the state bit, the remaining low as the address bit, the pointer consists of the address bit and the status bit. Skillfully apply the combination of address and state bit to achieve the control of empty and full flag bit. When both the address and state bits of the read-write pointer match, the read-write pointer undergoes the same number of cyclic movements, that is, the FIFO is in a null state (Figure 1 (a)); If the address bit of the read-write pointer is the same and the state bit is reversed, the write pointer loops more than the read pointer, and the flag FIFO

The status of the FIFO in Figure 1

2 32X8FIFO system Structure
       The 32x8fifo design described in this article uses a dual-body memory (FIFOMEMORY) structure (2). Each fifomemery has a 16x8 ram,rd-cntr3: and WR-CNTR3: respectively as read, write address, rd-cntr and wr-cntr respectively as read, write status bit. For the entire system, when the write signal (WrN) is valid, the data is written to the FIFO, and the two discrete memories are alternately written. When the read signal (RdN) is valid, the data is read out of the FIFO and alternately read from the two discrete memories. For the FIFO based on the monomer memory, there can be no write operation at the same time as the read operation, only after the end of the read operation. The alternating reading and writing mechanism used in this paper makes the 32x8 FIFO have the ability to read and write simultaneously, that is, one memory read operation can write to another, while one memory write operation can read the other memory. The 32X8 FIFO Data path is shown in block Diagram 3. There are two discrete memory fifomem (even) and fifomem (odd) in its structure. The FIFO Cntrl module controls read and write operations on these two discrete memories. The empty, full flag bits of the entire system are implemented by FIFOMEM (even) and fifomem (odd), empty, Full flag mem_full_even, Mem_empty_even, mem_full_odd, and mem_empty_odd, respectively. The RDN and WRN are the reading and writing control signals of the whole system, and the RSTN is the FIFO reset signal. At the same time, we can see that the 32x8 FIFO has 3 cycles of delay: input register, fifomemery and output register delay, fast access speed.

Figure 2 fifomemory block Diagram

Figure 3 32x8fifodatapath block diagram

3 32x8fifo Verilog HDL Implementation
Hardware Description Language Verilog HDL is a high-level description language widely used in the design of integrated circuits, which is suitable for many levels of design and description, such as behavior level, register transmission level and gate level, and has the advantages of simple, easy to read, easy to modify and independent of process. Therefore, the use of Verilog HDL language circuit design can save development costs and cycle.
All parts of this 32x8fifo are implemented with Verilog HDL code. Limited to space, the following list lists only the Fifomemery modules. Whole
32x8fifo design and application of the world famous EDA software supplier Synopsys Company's Designcompiler logic synthesis, and the application of Synopsys Company's simulation software VCS to do the simulation verification. (VCs is the VERILOGHDL simulation software of Synopsys Company) The FIFO memery module program list is as follows:

Module Fifo_mem (data,clk,rstn,wrn,rdn,empty,full);
inout [7:0] data;
Input Clk,rstn,wrn,rdn;
Output empty,full;

reg [4:0] wr_cntr,rd_cntr;
Wire [3:0] addr;
ram16x8 RAM (. data),. Addr (addr),. WrN (WrN),. OE (WrN));
Always @ (Posedge CLK or Negedge rstn)
if (!RSTN) wr_cntr<=0;
else if (!WRN) wr_cntr<=wr_cntr+1;
Always @ (Posedge CLK or Negedge rstn)
if (!RSTN) rd_cntr<=0;
else if (!RDN) rd_cntr<=rd_cntr+1;
Assign Addr=wrn?rd_cntr [3:0]: wr_cntr [3:0];
Assign empty= (wr_cntr [3:0] = = rd_cntr [3:0]) &&! (Wr_cntr[4]^rd_cntr[4]);
Assign Full= (wr_cntr [3:0] ==rd_cntr [3:0]) && (wr_cntr[4]^rd_cntr[4]);
Endmodule

4 Conclusion
Through the alternating reading and writing mechanism of two discrete memory, this paper realizes the simultaneous reading and writing function of the 32x8 FIFO, improves the speed of data access, and presents a novel method for the realization of empty and full flag bits. Using Verilog HDL Hardware description Language for circuit design, circuit synthesis and simulation using Synopsys Company's Designcompiler and VCs, circuit functions are verified.

Verilog implementation FIFO (reprint)