Verilog Introductory Experience (i) Always block use

1. Signal generation and the use of Always block precautions

1.1 Do not assign a value to the same variable within a different always block. That is, when a signal appears on the <= or = left, it can only be within one always block. (Detailed explanation see Verilog HDL and Digital circuit design P38)

It is important to note that when a signal is generated, all conditions that produce the signal should be considered within a always block.

1.2 Do not use both the blocking assignment (=) and the non-blocking assignment (<=) in the same always block.

1.3 Use block Assignment (=) when describing combinatorial logic using always blocks, using non-blocking assignment (<=) when describing timing logic with always blocks. A simple understanding can be that a blocking assignment is used within a level-sensitive always block, using a non-blocking assignment within an edge-sensitive always block.

1.4 Any variable that is assigned within the always block must be a register type (REG). That is, <= or = left signal, must be reg type, <= or = the signal on the right can be a reg type or wire type.

In addition, the port declaration is declared as input or inout type of port, can only be defined as a wire mesh type (wires), is declared as an output type of port, it can be defined as a wire mesh type, or register type (REG). If not defined, the wire mesh type is the default.

1.5 Always's sensitive list can include multiple level-sensitive events at the same time, as well as multiple edge-sensitive events, but not both power and edge-sensitive events. In addition, sensitive events that include both the rising edge of a signal and the falling edge sensitive event are also not allowed, because these two events can be combined into one level event.

2. Use of total CLK

The Edge trigger event in the Always sensitive list is a CLK signal, so the edge trigger event signal is defined on the CLK IO port when the UCF is developed, and sometimes the randomly allocated CLK IO port is implement. Need to be used in UCF

NET "Polin" clock_dedicated_route = FALSE; Polin for edge triggering event signal

Statement to circumvent the error.

So in a program, try to use the main CLK as the edge trigger signal of the always block. If some of the variables are to be generated by the edge of a signal, try to make the edge trigger signal as a condition, and then trigger with the main CLK when the variable is generated.

Routine: To get the LCD large screen POL signal 2-way, 8-frequency, 16-frequency ..., on the Control Panel toggle switch set different state, output polout switch to different pol input divider signal.

Train of thought, define a counter (CNT_POL) to count the input pol signal, the BIT0 bit of Cnt_pol is consistent with the POL input signal, Cnt_pol bit1 bit is 2 of the Pol Signal, and the BIT2 bit is 4 of POL, The BIT3 bit is Pol's 8-way, the BIT4 bit is Pol's 16 frequency ...

There are two methods of counter counting, one is to use Pol directly as an edge-triggered event count:

reg [8:0] Cnt_pol;

Always @ (Posedge Polin or Negedge rst)

if (!rst) Cnt_pol <= 0;

else Cnt_pol <= Con_pol +1;

(There is also a main CLK signal Clkin as the master clock for other signals)

The above method is relatively simple, but the polin as a CLK signal, can only be defined to the FPGA CLK IO port, and the implementation of error prone.

Alternatively, an edge-sensitive event that uses the main clock signal as a Cnt_pol count:

reg [8:0] Cnt_pol;

Reg Pold;

Wire cnt_event;

Always @ (Posedge Clkin or Negedge rst)

if (!rst) pold <= 0;

else Pold <= Polin;

Assign cnt_event = Polin & pold;

Always @ (Posedge Clkin or Negedge rst)

if (!rst) Cnt_pol <= 0;

else if (!cnt_event);

else Cnt_pol <= Cnt_pol +1;

This way, the program is more, but the entire program (including other parts) only Clkin is the CLK signal, avoids the above problem.

The explanation of this procedure: the mechanism of Cnt_pol counting is different from the first one, the first always block (register), the Polin signal is delayed, the pold signal is generated, pold and Polin in the phase difference of a clkin period. The Pold and Polin are then manipulated and assigned to cnt_event signals so that each high level of the cnt_event signal represents a Polin cycle. And then in the second always block, by judging the state of the cnt_event, to the Cnt_pol count. Simply put, the rising edge of the Polin is turned into a level state of the signal, which is then counted by judging the state of the signal level. The edge trigger signal used throughout the process is the main CLK.