Verilog language: It really is the language of division of Personality

The popular abdominal language artist is willing to reveal at the scene the performance of the man who was murdered by his partner, the abdominal language artist who took the soul. God is willing to really fall into the multiple personality, ordered to kill his wife and son of the puppet personality appeared. In order not to kill (let himself) the wife who had an affair with his disciple, the day would have offered the Commission to want to monitor, but the next morning, and the son really killed the incident occurred. God willing to confess is likely to be killed in the time when his consciousness is lost ... "(----" The truth is only one "" Detective Conan "has always been swaiiow like animation) This is the No. 806 back" the illusion of the abdominal teacher "introduction.

If a person has a double personality, or a split personality, what about language? Verilog language is really the language of division of personality. The former get books back has said that it is not easy to map wire types to combinatorial logic, but also to map reg types to sequential logic. In fact, the two concepts will intersect. In other words, wire types are most likely to be synthesized into combinatorial logic and may be integrated into timing logic, as is the case with Reg types.

What is ' Reg '? "The most Microsoft answer is: the registry file. This nature is true, but it violates the principle of "to which mountain, where to sing". The general "standard" answer is: register-type variable. Look at ' Reg ', not the abbreviation for ' register ' (register)? That's what most Chinese textbooks say.

In order to illustrate the white thing, please allow Old Monk to refer to the original text of the IEEE Verilog language:
"Assignments to a reg is made by procedural Assignments (see 6.2 and 9.2). Since The Reg holds a value between assignments, it can be used to model hardware registers. Edge-sensitive (i.e., flip-flops) and level sensitive (i.e., RS and transparent latches) storage elements can modeled. A reg need not represent a hardware storage element since it can also is used to represent combinatorial logic. "

To emphasize, the mapping between wire, Reg type and combinational logic, and temporal logic is given in table 1.

Table 1 mapping relationships between wire, Reg type, and combinatorial logic, timing logic

	Wire	Reg
Combinatorial logic	Can	Can
Timing logic	Can	Can

It can be seen that Reg is a "double-sided spy" work nature, in order to be able to "both ways", natural usage than wire to complex. The type wire is synthesized as a sequential logic. It's really wrong to write, not a table.

1. Level trigger, combination implementation
and Reg "Meng Jiao, jiao not away from Meng" is the keyword always, this to remember clearly. Others wire and assign is a husband and wife, Reg and always is a pair, do not confuse, this is not able to pull Lang match season.

The grammatical structure of "always" is:
Always @ (Sensitive_tabel)

Where Sensitive_tabel is called a sensitive list, which contains one or more trigger conditions for always internal operations. The character "@" is pronounced "AI" (at), when people email (e-mail) often used, not wordy.

As mentioned above, the standard façade can be said to be edge sensitive and level sensitive. For combinational logic circuits, all conditions in this sensitive list are level sensitive. Logically, always internal operations can be performed when the conditions within the sensitive list are met. However, a lot of logically feasible code, because there is no actual circuit support, is not possible.

In the Verilog language 95 version, the level-triggered sensitive list is
Triger1 or Triger2 or triger3 ...

Among them, triger1 and so on as the trigger signal. When the trigger signal level changes, the conditions in the sensitive list are met. If the trigger signal is a vector, then one of the bit signals changes, and the signal level is considered to be variable. By the Verilog 2001 version, this is simplified: "," and "or" can be used to segment sensitive events, and "*" can be used to represent all input signals, which prevents omissions. Example 1 shows some examples of consistent grammar.

"Example 1" Always and sensitive list
Always @ (triger1 or Triger2 or Triger3)//version and Version 2001
Always @ (Triger1, Triger2, Triger3)//version 2001
Always @ (*)//version 2001
Always-on modules with fully-level-sensitive lists are thought to be combinatorial logic. Once again, the digital circuit is working in parallel, and be careful not to use the word "execute", which is inaccurate. All the corresponding assign and always-led fast are parallel, and their order in the code is independent of the output result. In other words, example 2, the two-segment code is equivalent. In the code, the sensitive list sensitive_table1 and Sensitive_table2 correspond to operations operation_a and operations Operation_b.
"Example 2" always has a sequence of operations unrelated to the output result

Always @ (SENSITIVE_TABLE1) Operation_a Always @ (Sensitive_table2) Operation_b

Always @ (Sensitive_table2) Operation_b Always @ (SENSITIVE_TABLE1) Operation_a

Theoretically, there is only one line behind the assign, and the understanding of this parallel work is not difficult and will not be misunderstood. To always here, the general code will be followed by a lot of lines, without notice will be wrong.

2. Conditional judgment, branching lots
"The standard of C language evaluation of Verilog, as the fruit of the standard evaluation preserves." "But they do have a lot of similar writing, which is a very easy place to mislead learners.

The former instrument about "? : "Where the selection operation has been introduced, selection and branching are not limited in the general system." The Code method that is introduced there obviously produces difficulty reading----especially when conditions are much higher. In order to improve this problem, but also can be more in line with the previous habits of people, this book is old to introduce to the guest "if" and "case" the two people familiar with strangers.

First look at the code in the eye, the conditional statement if is in the form of three in table 2. Among them, condition such as the choice of conditions, operation and other representations of the corresponding operation. Please note that the expression "select" here is intended to correspond to the circuit, not intentionally to the other person's grandstanding.

Table 2 Format of conditional statement if

 	no branching	single-stage branching	multistage branching
form	If (condition) Begin     operations End	If (condition) Begin      operations_1 End Else Begin     operations_2 End	If (condition_1) Begin     operations_1 End Else if ( Condition_2  ) Begin     operations_2 End Else if ... ... Begin     operations_m End
correspondence circuit	timing circuit	timing circuit P align= "Center" > combinational circuit	timing circuit combination circuit

Table. 2 The "corresponding circuit" line also invites the donor to note that the IF statement in the condition of all the path coverage is not comprehensive, may produce a sequential circuit. For a variable of type Reg, it is necessary to keep the original value when the condition is not satisfied, and the combined circuit is not "self-assigned" (that is, the form of "a <= a"). When "hold" is needed, the pure combination circuit is not satisfied. Therefore, the integrated device will introduce a "latch". It is not the generalization that is required by the code. "The God of iniquity, from the evil can not live", you can only blame yourself, cry! This corresponding device is a latch, not the focus here, will be introduced later. Here is to say: to produce combinatorial logic, if the conditional path must be fully covered.

All paths to conditions in an if statement are not exhaustive and may result in a sequential circuit. This corresponding device is a latch, not the emphasis here, introduced later. Here is to say: to produce combinatorial logic, if the conditional path must be fully covered.

Example 3 is an example of a single-level conditional statement if application, whose function is to find the absolute value of the signed number. Where the input is a 8-bit signed number, the encoding is the complement; the output is the absolute value of the input value. The specific algorithm is:

"Example 3" absolute value arithmetic module
Module ABS
(
INPUT[7:0] Signed_value,
Output REG[6:0] Result
);

Definition for Variables in the module

Load other module (s)

Logical
Always @ (Signed_value)
Begin
if (Signed_value[7])
Negative number input
Begin
Result <= (~signed_value[6:0]) + 7 ' h01;
End
Else
Positive number or zero input
Begin
Result <= signed_value[6:0];
End
End

Endmodule

3. Multiple cases, parallel judgments
In the condition of a lot of time, with the IF statement to write or is very troublesome, do not make it is a conditional path coverage is not complete. At this time, you can choose the case package. The case statement is a multi-branch selection statement that Verilog the case statement provided by the language to directly handle the multi-branch selection. The multi-branch case has three forms, as shown in table 3.

Table 3 form of conditional statement case

	Case	Casex	Casez
Comparison mode	Comparison between sensitive expressions and various values is a congruent comparison	If the value of some bits of a branch expression is high impedance Z, then the comparison of those bits is ignored, not considered, and only the comparison of the other bits is concerned. Casez will match z/to any of them and will match any of them into z/?	In the Casex statement, this processing is further extended to the processing of X, that is, if the value of some bits of a side of the comparison is z or X, then the comparison of these bits is not considered. Casex will match z/?x to arbitrary, will also be arbitrary match into z/?/x, that is, directly ignore z/?/x
Form	Case (variable) costant_1: Begin Operations_1 End costant_2: Begin operations_2 End ...... Default Begin Operations_m End Endcase	Case ( variable ) costant_1 :     begin           operations_1     end costant_2 :     begin          operations_2     end ... Default:     begin          operations_m     End Endcase	Case (variable) costant_1: Begin Operations_1 End costant_2: Begin operations_2 End ...... Default Begin Operations_m End Endcase
Constant items	Each constant item is a constant value that determines the width and does not contain x and z; You can use "?" Indicates that there is no concern for this bit value	Each constant item is a constant value that determines the width and can contain x but cannot contain Z	Each constant item is a constant value that determines the width and can contain z but cannot contain Z
Constant example	3 ' b000:3 bit width full 0; 3 ' b0?0:3 bit width The second bit doesn't care, the other bits are 0	3 ' b000:3 bit width full 0; 3 ' b0?0:3 bit width The second bit does not care, the other bits are 0; 3 ' b00x:3 bit width minimum bit x, other bits 0	3 ' b000:3 bit width full 0; 3 ' b0?0:3 bit width The second bit does not care, the other bits are 0; 3 ' b00z:3 bit width minimum bit is not concerned, other bits are 0
Can be integrated	Can be integrated	Rely on integrated software	Rely on integrated software

A variable in a case bracket is called a control expression, and a constant in a case branch is called a branching expression. The control expression is usually expressed as some bit of the control signal, and the branch expression is represented by the specific state value of these control signals, so the branching expression can also be called a constant expression. When the value of the control expression is equal to the value of the branch expression, the statement following the spoke expression is executed. If none of the branch expression values match the value of the control expression, the statement following the default is executed.

The default item is optional, and there can be only one default item in a case statement. When a branch expression can override all the branching paths of a control expression, default can not be written. However, sometimes this full coverage is not so easy to see, so it is advisable to write the default, even if there is redundancy this default can never be implemented. Also please rest assured that this redundant comprehensive software will be removed, do not have to worry about wasting the circuit resources.

The value of the branching expression for each case sub-item must be different, otherwise there will be a contradiction (the same value for the expression, there are multiple execution scenarios).

After executing the case sub-item, the case statement is executed out of the structure of the case statement. (c-language-proficient prawns please pay special attention to this point, where the case operation after the execution does not have to write a break.) ）

In the process of comparison with a case statement expression, the comparison succeeds only if the value of the corresponding bit of the signal can be clearly compared, so the value of the branching expression of the case sub-item is detailed.

The value of all expressions of the case statement must have equal bit widths, so that only control expressions and branch expressions can be compared to the corresponding bits. A frequent mistake is to use ' bx, ' BZ to replace n ' bx, n ' BZ, so it is wrong to write, because the default width of the signal x, Z is the machine's byte width, usually 32 bits (where n is the bit width of the case control expression).

When a branch expression does not completely overwrite the entire branching path of the control expression, you are always lazy without writing the default case, which may produce a sequential logic latch, which is similar to the conditional if statement. Example 4 is an example that shows the importance of default. However, the "LD" in Figure 1 is already a component of a sequential circuit, beyond the scope of this chapter.

"Example 4" case statement condition coverage not fully generated will be integrated out latch
Code Listing 1: Combining logical circuit notation
Module Case_full
(
INPUT[7:0] Number,
INPUT[1:0] Select,
Output REG[7:0] Result
);

Load other module (s)

Definition for Variables in the module

Logical
Always @ (*)
Begin
Case (SELECT)
2 ' b00:
Begin
Result <= number + 8 ' b0000_0001;
End
2 ' B01:
Begin
Result <= number;
End
2 ' B10:
Begin
Result <= number-8 ' b0000_0001;
End
Default
Begin
Result <= 8 ' b0000_0000;
End
Endcase
End
Endmodule

Figure 1 Example 4 integrated circuit diagram (all of the combined logic)

4. Multi-channel selection, an example
Data selector (also known as: Multiplexer, English: multiplexer, Shorthand: MUX), is a device that selects a signal from a multiple input signal as output. The electrical symbol 2 shows.

Figure 2 Electrical symbols for the data selector

The logical functions of the data selector are:

Note that the input I0, I1, and SEL, and the output o are all 1 bit wide signals. The corresponding boolean-logical expression is

The corresponding Verilog code is:
1) use? : An expression
Input SEL;
Input I0;
Input I1;
Output O
Assign O = (SEL)? (I0): (I1);
What is the key part of the code?  : An expression whose grammatical structure is (logical expression)? (value 0): (value 1);

Therefore, the above code satisfies the function of the data selector in the digital circuit.

2) Use if keyword
If (SEL = = 1 ' b0)
Begin
O = I0;
End
Else
Begin
O = I1;
End
3) Use case keywords
Case (SEL)
1 ' B0:
Begin
O = I0;
End
1 ' B1:
Begin
O = I1;
End
Endcase

In many cases, you need to select the input bit width greater than 1, this time as long as two to select the input and the output of the bit width consistent, you can still implement the function (the following 8-bit input as an example). At this point the Verilog code has little variation in addition to the interface bit width of the module:

Input SEL;
INPUT[7:0] I0;
INPUT[7:0] I1;
OUTPUT[7:0] O
Assign O = (SEL)? (I0): (I1);

Of course, if or case statements can also be achieved, I believe that the reader extrapolate ability, it is not listed.
Many readers may feel that the author is very verbose, but in fact, Figure 3 is a multi-input data selector electrical schematic diagram.

Figure 3 Circuit schematic diagram of a data selector

Seems to be a logical one. The reason why I still bother to draw out here is to ask the reader to see the difference between the multi-bit and 1-bit implementations. If the eyes are not Gui, it can be seen that multiple data selectors are parallel permutations of several 1-bit data selectors. Given the latency problem described earlier, it is important to remind the reader that the skew (inter-line delay) of the input and output signals may cause problems in the design when the number of bits is high (not 8 bits in the example).

Another common scenario is that the input has more than two signals, or that it needs to be selected in more than two signals, which is called a high-order data selector (the number of bits in the SEL is called the order of the data selector). Usually the number of inputs is a power of 2, at this time the selection signal sel is not only a 1-bit signal, this is easy to understand. In theory, high-speed higher-order data selectors can be completed by expanding the Boolean-logical expression method. For example, a randomly selected Boolean logical expression of 2 order (that is, 4 input signals and SEL 2-bit variables) is:

Among them, I0, I1, I2 and I3 are input to the device, S0 and S1 are low bits and high bit of the SEL signal.
This formula is not easy, if it is a 10-order God horse Data selector, the length of such a formula is not difficult to imagine. Therefore, in engineering, the low-order data selector is generally used in series to realize the high-order data selector. Figure 4 is an example of implementing a 2-step data selector with a 3 1-step data selector.

Figure 4 High-order data selector with low-order data Selector

For Verilog code for high-order data selectors, it is generally advisable to take the form of case. The 2-order data Selector In Example 3 can be implemented with the following code:
Case (SEL)
2 ' b00:
Begin
O = I0;
End
2 ' B01:
Begin
O = I1;
End
2 ' B01:
Begin
O = I2;
End
2 ' B11:
Begin
O = I3;
End

Endcase
This is:
“
The combination of logical integration, key grammar has experience. No matter the theoretical mathematical river, the circuit optimization by synthesis.
I have a story of my own music, pry old monk Samigo. The report organizes jealousy, Mahayana people smiling.
”

and non-net original content, declined reprint!

Series Summary:

One: Warm so know new: from the circuit, to Verilog!

Second: Verilog programming can not be accomplished overnight, language level pay attention to "the name is the word shun"

Third: Digital logic is not a small glimpse, circuit door Unified Lake

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About the author Garfield

Ten years of sleep, Ph. D. has been engaged in research and development of wireless communication products for ten years after graduation. Learn about standard protocols, receiver algorithms, and system architecture and development for W-CDMA, TDS-CDMA, and LTE. Engaged in the FPGA IP core design work on W-CDMA, also completed W-CDMA and TDS-CDMA receiver theory Research and link simulation work. Combined with the above work, finally selected the wireless communication system design and standard design work. Currently has more than 100 authorized invention patents, is a communication industry standard document of the first author, also has the patent idea is written 3GPP protocol. Published works "IP Core Records".

Reprinted from: Http://www.eefocus.com/fpga/365722/r0

Verilog language: It really is the language of division of Personality