Verilog Small Sense

Today, my classmates told me that the FIR filter timing is not up, he said that the multiplier delay is too large, left to move, but the simulation of the left shift or 2 cycle to move, the shift register code is as follows:

Always @ (Posedge CLK)

Begin

A <= {in[8:0],0};

Out <= A;

End

After seeing this code, I immediately realized that this was done through two cycles, in the first cycle, although a value was given to a, but the data obtained from the out is the data of the previous period, then in the final analysis, this is an issue of blocking assignment and non-blocking assignment.

From this problem, I have a deeper view of blocking and non-blocking. In fact, when the CLK rising edge is approaching, the current value of the data is all lanch to the left of the equals sign.

Verilog Small Sense