Verilog Study Notes Basic grammar (eight) Structure Description Statement

Any process in Verilog can belong to the following four kinds of structure description statement;

1) initial;  2) always;   3) Task; 4) function;

1) initial statement;

The number of initial and always in a program is unrestricted, and they all start running at the beginning of the simulation. Initial is executed only once, and the always statement is repeated activity until the end of the simulation activity, but always the process is running quickly, it depends on whether the trigger conditions are satisfied, meet the run once, and then meet again to run until the end of simulation.

Format:

Initial

Begin

Statement 1;

Statement 2;

...

Statement N;

End

There can be multiple initial blocks in a module, and they all run in parallel. Initial blocks are often used for the writing of test files and virtual modules to generate simulation environments such as test signals and set up signal recording.

2) Always description statement

Its declaration format is as follows:

Always < Timing control > < statements >

If always there is no timing control, an emulator deadlock is generated. such as: always areg=~areg; This results in a 0-delay infinite loop transition, when a simulation deadlock occurs.

The timing control of always can be either an edge trigger or a level trigger, and a single signal can also be linked with more than 10 signals in the middle with keywords or.

A) always @ (Posedge clock or posedge reset)

Begin

....

End

B) always @ (Posedge clock or posedge reset)

Begin

....

End

In the above, A is a two-edge triggered always as long as one of the edges appears, immediately executes the process block. B is a B c three signal level triggered, as long as any one in a B c changes, from high to low or from low to high will execute the process block.

Always-on edge-triggered blocks often describe timing behavior, such as finite state machines, which typically correspond to the structure of register groups and gate-level combinatorial logic. The always block of level triggering is often used to describe the behavior of combinatorial logic.

in the Always statement, a list of multiple event names or signal names linked by a keyword or is called a sensitive list. use keywords or or ', ' to denote this relationship. If you enter more logical variables, it can be tedious and error-prone to write sensitive lists. In this case, Verilog can be used with @* and @ (*), which indicate that changes to all the input variables in the subsequent statement block are sensitive.

Level-sensitive timing control:

Verilog uses the keyword wait to indicate that the condition for waiting level sensitivity is true:

such as: Always

Wait (count_enabal) #20 count = count+1;

In this example, the emulator continues to see the value of Count_enable, whose value is 0, does not execute the following statement. If the value is 1, then 20 units are executed after this statement, and if Count_enable is always 1, then count is +1 per 20 units of time.

Verilog Study Notes Basic grammar (eight) Structure Description Statement