VHDL top-level call Verilog module

When VHDL calls the Verilog module, add "VERILOGMODELGM:" Before instantiating the module.
VHDL Call Verlog:
Verilog module://verilog Port declaration in the underlying file
Module M (a,b,c);
Input A, B;
Output C;
...
The Endmodule call is as follows:
Compoent m--VHDL The original example in the top-level file
Port
A:In std_logic;
B:in std_logic;
C:out Std_logic
);
End Compoent

Begin--VHDL mapping in top-level files verilogmodelge:m//(I don't have to do my own experiment.) , using the error, it is estimated that the software has become clever ~)--to this sentence to reserve views ZJW port Map
(...
)
...
End
Call Verilog in VHDL: Instantiate + map
In the Verilog call VHDL words: As long as the mapping