Virtex6 PCIe lite basic concepts (1)

Virtex6 PCIe lite basic concepts (1)

Document version	Development Tools	Test Platform	Project name	Date	Author	Remarks
V1.0	Ise14.7	DBF Board	Day2/PCIETest1	2016.03.31	Lutianfei	None

References:
Spartan 6 PCIE_V2.4 real tutorial (2) fast-paced fpga_pciedesign Tutorial: v6_pcie_ug5171_pci1_express1_structure guide: xapp1052.pdf

Common interface speed 2 Transaction Processing Layer Protocol understanding 1 Transaction Layer Space Description 2 configuration space Overview 21 configuration space register description 22 PCI bus configuration overview 3 BAR space Overview 31 BAR space and DMA space ing link Example 4 Transaction Processing Layer overview 41 memory read/write requests TLP Header Format 42 complete packet header format 33 configure read/Write Request Header Format 44 message Request Header Format

(1) Common interface speed

  <喎?http: www.bkjia.com kf ware vc " target="_blank" class="keylink"> VcD4NCjxoMiBpZD0 = "Two Transaction Processing Layer Protocol understanding"> (2) Transaction Processing Layer Protocol understanding 2.1 description of Transaction Layer Space1. PCI configuration space: it is mainly used to provide the system with basic information about the device itself, and to accept the system's control and query of the global status of the device. 2. I/O space: mainly including DeviceOf Control RegisterAnd Status RegisterIt is generally used to control and query the working status of a device and exchange a small amount of data. 3. memory space: it mainly includes memory, video memory, extended ROM, and device buffer. It is generally used to store a large amount of data and exchange data blocks. 4. Message Space: The time signal mechanism space for transmitting messages.

 

2.2 configuration space OverviewPCI devices can be accessed by other primary devices only after the system software initializes the configuration space. After the configuration space of the PCI device is initialized, the device has an independent pci bus Address space on the current PCI bus tree, that is, BAR (Base Address Register) the space described by the register. 2.2.1 description of configuring spatial registers

Vendor ID: Representative of the manufacturer of PCI devices Device ID: Indicates the specific device generated by the PCI vendor. Revision ID: Record the version number of the PCI Device, which can be seen as an extension of the Device ID register. Class Code: Used by system software to identify the current category of PCI devices.
Base Class Code: Classifies PCI devices as graphics cards, NICS, and PCI bridges. Sub Class Code: Further segment these devices Interface: Programming Interface Header Type: There are 8 digits, of which
The 7Bit: 1Indicates that the PCI device is Multiple FunctionsDevice, which is 0Indicates Single FunctionDevice. The 6 ~ 0Bit: 0: PCI AgentThe configuration space of the device (Common PCI settings ); 1: Configuration space used by PCI Bridge Subsystem ID, Subsystem Vendor ID: Similar to Device ID and Vendor ID, but further subdivided.
Capabilities Pointer: PCIe devices must support this register to store extended configuration information related to PCI devices. Interrupt Pin: PCI has passed four INTA pins: INTA #, INTB #, INTC #, INTD # Base Address Register0 ~ 5: Save the base address of the address space used by the PCI device. The base address stores the address of the device in the PCI bus domain. Command: The command register of the PCI device. The value is 0In this case, the PCI device can only accept Configure request bus transactionAnd cannot accept any storage or I/O requests. The system software must properly set the register before it can access the memory or I/O space of the device. (For details about the Register function, refer to PCI + EXPRESS architecture guide p49) Status: The vast majority are read-only bits, saving the status of the PCI device.

 

2.2.2 overview of PCI bus ConfigurationType00 configuration request: the PCI Agent device or PCI bridge directly connected to the HOST master bridge or PCI bridge. Type01 configuration request: access a PCI Agent device or PCI bridge that is not directly connected to at least one PCI bridge.

 

2.3 BAR space OverviewAfter the PC is started, the BIOS detects the peripherals found. For PCIe (PCI) devices, the BIOS detects the number of BAR spaces on the board, the size of each space, and allocates addresses for these BAR spaces. For a PCI device, it can "see" that the PCIe board space is only BAR space and can only access these BAR spaces. The Board can send valid PCIe TLP packets and receive responses from the PC. However, the PC Access Board is limited to BAR space. 2.3.1 example of BAR ing between BAR space and DMA Space

 

2.4 Transaction Processing Layer Overview

TLP (Transaction Layer Sepcification) consists of three parts: frame header, data, and summary (or ECRC ). TLPHeader labelLong3 or 4 DW, The format and content change with the transaction type;Data endThe data segment defined for the TLP frame header. If the TLP does not carry data, the segment is empty.Digest segment(Optional) is a CRC calculated based on the header label and data field, and becomes an ECRC.IP Core Filling. Therefore, PCIe processing is represented at the user layer as processing TLPHeader labelAndData Segment.

2.4.1 TLP headers for memory read and write requests

Fmt and Type: Specifies the transaction type, header length, and whether data loads exist.

Posted and Non-PostedPackage

Non-posted: The response package for the request to return the completion; Posted: return the response package without the completion. For example, the above memory write request package and Message package are both affiliated with the posted package.

** Length: 1 ~ 1024DW; Value: ** 0: 1024DW

DW BE:

Requester ID: PCIe device that contains "generate this TLP packet"Bus Number),Device Number),Function Number)

Tag: The Requester ID and Tag are combined to form the Transaction ID. During the same time period, each Non-Posted data request TLP sent by the PCIe device must have a unique Transaction ID. That is, the Tag must be unique.

 

2.4.2 complete packet header format

* Byte0 ~ 3.Storage, ConfigurationThe fields corresponding to the request message have the same meanings.
*Completer ID: This field stores the ID number of the PCIe device that sends the completed message.
*Byte CountRecord how many bytes of data the source device needs to obtain from the target device to complete all data transmission.
*Lower Address: The receiving end must use the memory to read and write the Low Address field of TLP to identify the starting Address of a TLP containing data.

 

2.3.3 configure the read/write Request Header Format

Configure the request TLP 0th ~ 7 bytes is similar to memory requests, 8th ~ Of the 11 bytes BUS, DeviceAnd FunctionThe Number of the target device that the TLP accesses. Ext RegisterAnd ReigisterNumber stores the Register Number. Other fields of the configured request message must be the following values:

 

2.4.4 message Request Header Format

The PCIe bus specifies the following types of message messages:

INTx Interrupt Signaling INTx Interrupt information package Power Management function. Error Signaling Error message package Locked Transaction Support lock Transaction Support Slot Power Limit Support Vendor-Defined Messages manufacturers' custom information

INTx interrupt message