Vivado use error and advanced XDC constraint skills--clock chapter __FPGA

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Xilinx's new generation of Design Suite Vivado introduces a completely different set of constraint file Xdc, which differs greatly from the UCF supported in the previous generation of product Ise in many rules and techniques, bringing many additional challenges to users. Xilinx tool experts tell you, in fact, using good xdc is easy, just master a few core skills, and always keep in mind: Xdc grammar is actually TCL language.

Advantages of Xdc

XDC is a shorthand for the Xilinx design Constraints, but its basic grammar comes from the industry's Unified constraint specification SDC (first proposed by the Synopsys company, hence the name Synopsys design Constraints). So the relationship between SDC, Xdc and Vivado Tcl is shown in the following illustration.

The main advantages of XDC include: Unified front and rear constraint format, easy to manage; can be entered and executed in real time like a command; Allow incremental setting of constraints, speed up debugging efficiency, high coverage, scalability, high efficiency, industry unity, good compatibility, portability strong;

Xdc is essentially a TCL language, but it only supports basic TCL syntax such as variables, lists, and operators, and syntax for other complex loops and file I/O can be supplemented by a Tcl file in Vivado. (The reader who is interested in Tcl's topic can refer to another article by the author, "Tcl's application in Vivado")

The main differences between XDC and UCF are two points: Xdc can be read as a whole file by the tool as UCF, or it can be executed directly as a separate command in the implementation process. This determines that the XDC also has the characteristics of TCL command, that is, the constraints entered later in a conflict will overwrite the constraints entered before (the priority of the sequence exception will be detailed in the next section). In addition, unlike UCF is the way to read all the processing, in Xdc, the constraint is read a implementation, so the order is very important, such as to set the IO constraint, the corresponding clock must first be created. UCF is completely based on the FPGA point of view, therefore, by default, all clocks are considered to be asynchronous and do not span clock domain timing analysis unless the declaration is synchronized. Xdc on the contrary, the genetic background of the ASIC world determines that all clocks default to full synchronization, In the absence of time series exceptions, the tool proactively analyzes the path of each cross clock field.

the basic grammar of Xdc

The basic syntax of XDC can be divided into three categories: Clock constraint, I/o constraint and time constraint. According to the suggestions of the baseline part of the ultrafast design methodology of Xilinx (UG949 in detail), the Order of constraint on a design can be carried out in sequence according to these three kinds of constraints. This article does not provide a detailed explanation of the basic XDC syntax that can be found in the Help document and focuses on the use of methods and techniques.

clock Constraint

Clock constraints must be first created, for the 7 series FPGA, the port in the main clock and the GT output RXCLK/TXCLK must be created by the user Create_clock. The derivative clock is divided into the following two categories: MMCM/PLL/BUFR output clock can be automatically deduced by Vivado, without user creation. If the user only wants to change the name of the derivative Bell, the rest of the frequency, etc. are automatically deduced by the tool, you only need to specify three option, the rest does not write: Create_generated_clock [-name arg] [-source args] [-master_clock ARG] tool does not automatically derive the case of derivative clocks, including the use of registers and combinational logic to build the divider, etc., must be created by the user using Create_generated_clock.

I/O constraints

In the initial stage of design, it can be used without I/o constraints, so that the tools focus on meeting the timing requirements within the FPGA. When the order requirements are basically satisfied, plus I/O constraints run implementation.  I/O constraints in Xdc have the following points to note: Port timing requirements that do not have any I/O constraints are considered infinity. The Set_input_delay/set_output_delay in xdc corresponds to the OFFSET in/offset out in UCF, but the opposite view.  The OFFSET In/offset out is to constrain the port timing from the angle of the internal delay of the FPGA, and the Set_input_delay/set_output_delay is constrained from the system angle. Typical I/O timings, including system synchronization, source synchronization, SDR and DDR, and so on, are examples of the XDC templates in the Vivado graphical interface. After version 2014.1, there is also a timing Constraints wizard available for use.

Timing Exception Constraint

Time series exception constraint including Set_max_delay/set_min_delay,set_multicycle_path,set_false_path, such constraints, in addition to meeting the priority of XDC, but also by their own priority constraints. A general principle is that for the same path, the more specific priority is given to the constraint target description. The different timing exception constraints and the precedence of different conditions in the same constraint are as follows:

For example, the following two xdc are executed sequentially, although the second is final, but the tool still determines that the first constraint set 15 is the max delay value of the path between CLK1 and Clk2.

For example, the following four sequential exception constraints are followed for the diagram path, and the winner will be the second one. However, if you add the last constraint, false path has the highest precedence and replaces all of the previous time exception constraints.

Efficient clock constraints

Constraints are ultimately designed to design services, so to use a good xdc need to understand the circuit structure and design requirements. Next, we use the clock structure in the common FPGA design to illustrate the XDC's constraint techniques in detail.

0 Beginnings of the time series

The "0 starting point" of the first order of the primary clock defined by Create_clock is automatically ignored by the tool before the upstream path delay. So it's important that the main clock is created at which point. The following diagram shows the structure to example, the FPGA input port and the BUFG output port to create a master clock, in the timing report, the path delay is completely different, it is obvious that Sysclk_bad report lacks the previous period of delay, the timing report is not credible.

the order of the clock definition

The definition of the clock also follows the general priority of the XDC/TCL, that is, at the same point, the user-defined clock overwrites the clock that the tool automatically infers, and the defined clock overrides the first defined clock. To coexist, you must use the-ADD option.

The output of BUFG in the above example driven by the user defines a derivative clock clkbufg, this derivative clock will cover the original SYSCLK. In addition, the diagram BUFR works in bypass mode, and its output does not automatically create derivative clocks, but defines a derivative clock clkbufr on the output side of the BUFR, and after using the-add and-master_clock options, At this point there will be two overlapping clocks sysclk and CLKBUFG. The TCL command, as follows, validates our reasoning.

synchronous clock and asynchronous clock

Unlike UCF constraints, in xdc, all clocks are considered to be related by default, meaning that all existing sequential paths in the table are Vivado analyzed. This also means that the FPGA designer must tell the tool through constraints which paths are not parsed and which clock domains are asynchronous.

As shown in the figure above, two main clock Ssclkin and SYSCLK from different ports into the FPGA, and then through a different clock network transmission, to set them to asynchronous clock, you can use the following constraints:

Among them,-include_generated_clocks represents that all derivative clocks are automatically set with their primary clock, which is an asynchronous relationship with the clocks of other groups. Without this option, only the constraint of the clock relationship is applied to the main clock level.

overlapping (single point multiple) clocks

Overlapping clocks are multiple clocks that share exactly the same clock transmission networks, such as two clocks, which are output after a MUX selection, and are common in designs with multiple operating modes.

As the following illustration shows, clk125 and clk250 are Clkcore_buf's two input clocks, without constraining the clock relationship, Vivado analyzes the diagram paths across the clock domain (overlapping clocks). Such timing reports are not credible even if they are not breached, since clk125 and clk250 cannot simultaneously drive the sequential elements on the path. Doing so also increases the elapsed time and affects the final implementation effect.

If clk125 and clk250 do not drive other sequential components except through the same fan after the clkcore_buf, all we have to do is to make up for the constraint of the clock relationship.

In many cases, except for a common fan out, one of the clocks or two drives other timing components, the recommended practice is to create two overlapping derivative clocks on the clkcore_buf output and constrain their clock relationships to-physically_exclusive means it is impossible to pass at the same time. This can maximize the constraint coverage and is not possible in Ise and UCF.

Other advanced Constraints

The constraint of the clock is the foundation of XDC, mastering the clock constraint, and is also the basis of xdc constraint skill. Other advanced constraint techniques, including complex CDC (Clock Domain Crossing) Constraints and interface timing (SDR, DDR, System synchronization interface, and source sync interface) Constraints, are also noteworthy.

Reproduced in this paper-XILINX Shanghai, ALLY ZHOU