What is the difference between wire and Reg? Reprint the Great God!

Note This article refers to the original: http://www.cnblogs.com/thymon/archive/2010/06/09/1754541.html

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In short, there are two uses of hardware description Language: 1, simulation, 2, synthesis.

For wire and Reg, it is also to be considered from these two angles.
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From the point of view of simulation,HDL language is faced with compilers (such as Modelsim, etc.), equivalent to the software idea.
Then:
Wire corresponds to continuous assignment, e.g. assign
Reg corresponds to procedure assignment, such as Always,initial

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From a comprehensive point of view, the HDL language is faced with the integration device (such as DC, etc.), to be considered from the perspective of the circuit.
Then:
1, wire type of variable synthesis out is generally a conductor;
2. The reg variable has two cases in the Always block:
(1), always after the sensitive table is (a or B or C) Form, that is , without the clock edge, synthesis or combination logic
(2), always after the sensitive table is (Posedge clk) Form, that is, with the edge, the general is the timing logic, will contain triggers (flip-flop)

In the design, the input signal in general you do not know whether the upper level is the register output or the combination of logic output, then for this level is a wire, that is, cable type. And the output signal is your own decision is the register output or combination logic output, wire type, Reg type can be. But in general, the entire design of the external output (that is, the output of the top -level module), the requirements are register output, more stable, fan-out ability is also good.

Fan out ability: As a beginner, I think of myself as a driving ability. The textbook seems to say that a signal has been assigned to several signals ~ ~ ~ ~ ~, or go back and read the textbook.

Why do you define wire in Verilog?

There are several case variables that need to be defined as wire.
First. Assign statements
For example:
Reg A, B;
Wire And_result;
...
Assign And_result =a&&b;//This is obviously no logical line
You can try to define a wire as Reg. The integrated device will error.

Second. The output must be in wire when the component is instantiated
For example:
Wire dout;

Ram U_ram
(
...
The signal from the. Out (dout)//out is transmitted to dout, so why can't we use the Reg type? Is it not logical that dout is an input to another module??? Let's just say that!
...
);

Wire According to the above definition of foreign textbooks: wires for the non-logical connection . The wire itself is not logical, so the input is what the output is ( this is not to think that this is the nature of wires). So you try to assign a value to the wire variable with the always statement. The integrated device will make an error. Then you might ask. Assign C =a&&b is not the assignment of wire? Not really. When synthesizing the synthesis, the a&&b is synthesized into ab through a door. and C just connects to the line with the gate output. It is && that is really integrated with the door. Rather than c.

Abstract
Verilog's most frequently asked question: "When should I use wire? When should I use Reg?"

Introduction
In the larger sense, wire and Reg are similar to the changes in the C + +, But if the change is to be placed inside the begin...end, the variable has to use Reg, and wire is used outside of Begin...end.

In addition to using wire, it is not necessary to match assign;reg.

The Input,ouput,inout preset values are wire.

If the wire and Reg use the wrong place, compiler will be reminded, so don't worry too much.

A very important observation, the use of reg in Verilog, does not mean that the register is after the synthesis. If you use Reg in a combined circuit, the composition is still net, only the Reg is used in the timing circuit, and the synthesis is then represented as a register in the flip-flop form.

What is the difference between wire and Reg? Reprint the Great God!