DDR3 is expected to be born next year
The speed is soaring! AMD's AM2 Interface K8 architecture Processor introduced support for the highest DDR2 800, and Intel released its long-awaited Conroe processor on July 23 and carried out the largest "terrorist attack" in history, and the computer market appeared to have entered the DDR2 800 in 2006 ahead of time. RD600 supports 1500Mhz front-end bus overclocking, but at the Computex 2006 Taipei Computer Show, RD600 seems to "temporarily give up" DDR3 memory support to support DDR2 1066 of memory, so DDR3 memory failed to meet the audience in 2006.
DDR3 compared to DDR2 has a lower operating voltage, from the DDR2 1.8V Landing to 1.5V, better performance and more power saving; DDR2 4bit pre-read upgrade to 8bit prefetching, DDR3 is currently up to 1600Mhz speed, As the fastest DDR2 memory speed has been raised to 800mhz/1066mhz speed, the first DDR3 memory modules will jump from 1333Mhz. At the Computex exhibition we have seen a number of memory vendors exhibiting 1333Mhz DDR3 modules.
DDR3 in DDR2 based on the use of 8bit prefetching design, point-to-point topology, and 100nm below the production process, such as the latest technology, then DDR3 and DDR2 in the end have those different places? What are the performance improvements compared to DDR2 enthusiasts and players?
More flexible burst length
Because of the DDR3 8bit, the burst transmission cycle is fixed to 8, and for DDR2 and early DDR architecture system, BL=4 is also commonly used, DDR3 to this increase a 4bit Burst chop burst mutation mode, that is, a bl=4 read operation plus a bl= 4 write operation to synthesize a bl=8 data burst transmission, then can control this burst mode by A12 address line. It should also be noted that any burst operation will be prohibited in DDR3 memory and not supported, and replaced by more flexible burst-transfer control
Improved addressing timing
Just as the number of delay periods increases as the DDR2 from the DDR transition, the CL cycle of DDR3 will also improve compared to DDR2. The CL range of DDR2 is generally between 2~5, while DDR3 is between 5~11 and the design of additional delay is also changed. The range of Al at DDR2 was 0~4, while the DDR3 had three options, namely, 0, CL-1 and CL-2. In addition, DDR3 has added a new timing parameter: "Write Delay", which will be based on the specific frequency of work.
New Reset Feature
Resetting is an important new feature of DDR3, and a pin is specially prepared for this purpose. The DRAM industry has long demanded that this feature be added, and now it is finally implemented on the DDR3. This pin will make the initialization of the DDR3 easier. When the reset command is in effect, the DDR3 memory stops all operations and switches to the smallest active state to conserve power.
During reset, DDR3 memory shuts down most of the intrinsic functions, all data receivers and senders will be closed, all internal programs will be reset, the DLL and clock circuits will stop working, and any movement on the bus is ignored. This will enable DDR3 to achieve the most energy-saving purposes.
New ZQ Calibration function
ZQ is also DDR3 a new pin with a 240 ohm low tolerance reference resistor on the PIN. This pin uses a set of commands to automatically check the end resistance of the data output driver and the ODT through the on-chip calibration engine.
When this instruction is issued by the system, will use the corresponding clock cycle, after the power and initialization of 512 clock cycles, after exiting from the refresh operation with 256 cycles, in other cases with 64 cycles, to the resistance and odt resistance to calibrate.
The voltage is divided into two and point-to-point connections.
In the DDR3 system, the reference voltage signal vref which is very important for the work of the memory system will be divided into two signals, namely the VREFCA of the command and address signal service and the VREFDQ for the data bus, which will effectively improve the signal-to-noise level of the system data bus.
This is an important change to improve the performance of the system, but also a key difference between DDR3 and DDR2. In a DDR3 system, a memory controller deals with only one memory channel, and this memory channel can only have one slot, therefore, between the memory controller and the DDR3 memory module is a point-to-point relationship, or point to the two-point relationship, thereby greatly reducing the address/command/control and data bus load. In the memory module, similar to the DDR2 category, there are standard DIMMs, So-dimm/micro-dimm, fb-dimm2, where the second-generation FB-DIMM will adopt a higher-specification AMB2 advanced memory buffer.
DDR3 the future, a bright
64-bit architecture-oriented DDR3 obviously has more advantages in frequency and speed, in addition, due to the DDR3 of the temperature automatically from the refresh, local refresh and other functions, in power consumption is also much better than DDR2, so it may be the first to be welcomed by mobile devices, It's like the laptop and the server that are the first to greet DDR2 memory.