What is the difference between synchronous logic and asynchronous logic?

1. What is the difference between synchronous logic and asynchronous logic? 
Synchronization logic is a fixed causal relationship between clocks. Asynchronous logic does not have a fixed causal relationship between clocks.
Circuit design can be categorized into synchronous circuit and asynchronous circuit design. The synchronous circuit uses the clock pulse to synchronize the sub-system, while the asynchronous circuit does not use the clock pulse for synchronization. The sub-system uses a special "start" and "finish" signal to synchronize the sub-system. Asynchronous Circuits have the following advantages: no clock skew problem, low power consumption, average efficiency rather than the worst efficiency, controllability, combination and reusability. As a result, research on asynchronous circuits has increased rapidly in recent years., in this paper, the Intel Pentium 4 processor design has begun to adopt asynchronous circuit design.
An asynchronous circuit is a combination of Logical Circuits Used to generate read/write control signal pulses of address decoder, FIFO, or ram. Its logical output has nothing to do with any clock signal, the glitch generated by decoding output is usually monitored. A synchronous circuit consists of a timing circuit (register and various triggers) and a logic circuit. All its operations are completed under strict clock control. These time series circuits share the same time clock CLK, and all state changes are completed at the rising (or descending) side of the clock.

2. What is the logic of "line and"? What are the specific requirements on hardware features for implementing it?
Line and logic are functions that can be achieved by connecting two output signals. On the hardware, the OC gate is used for implementation (drain or open collector). Because the OC gate is not used, the filling current may be too large, and the logic gate is burned out, at the same time, an upstream resistor should be added to the output port. (Line or drop-down resistor)

3. What is the difference between setup and holdup time. 
Setup/hold time is the time requirement between the input signal and the clock signal of the test chip. The creation time refers to the time when the trigger's clock signal remains unchanged before the rising edge. The input signal should arrive at the chip at t time in advance of the clock rising edge (for example, the rising edge is valid), which is the time-setup time. if the setup time is not met, the data cannot be pushed into the trigger by the clock. Only on the rising edge of the next clock can the data be pushed into the trigger. The holding time refers to the time when the trigger's clock signal remains unchanged after the rising edge. If the hold time is not enough, data cannot be pushed into the trigger.
Setup Time and hold time ). The time when the data signal is created is the time before the clock edge. The retention time refers to the time when the data signal remains unchanged after the clock jumps to the edge. If the creation and retention time are not met, DFF will not be able to correctly sample the data and stability will occur. If the duration of the data signal before and after the clock is triggered exceeds the set-up and keep-up time, the excess time is called the set-up time margin and the set-up time margin respectively.

4. What is competition and adventure? How to judge? How to eliminate it? 
In the combination logic, due to different latencies in the input signal path of the door, the inconsistent arrival time is called competition. Glitch is called adventure. If there is an opposite signal in the Boolean expression, competition and risk-taking may occur. Solution: one is to add a Boolean elimination item, and the other is to add a capacitor outside the chip.

5. Do you know the common logic levels? Can TTL and COMS levels be directly interconnected? 
Common logic levels: 12 V, 5 V, 3.3 V; TTL and CMOS cannot be directly interconnected, because TTL is between 0.3-3.6v, while CMOS is available in 12 V and 5 V. The CMOS output can be directly connected to TTL. To connect TTL to CMOS, you need to add an upstream resistor to the output port to connect to 5 V or 12 V. The high and low levels of CMOS are: VIH> = 0.7vdd, devil <= 0.3vdd; voh> = 0.9vdd, vol <= 0.1vdd. TTL: VIH> = 2.0 V, devil <= 0.8 V; voh> = 2.4 V, vol <= 0.4 V. you can use CMOS to directly drive TTL. After pulling, TTL can drive CMOS.

6. How to Solve the sub-steady state.
The sub-Steady State means that the trigger cannot reach a verifiable state within a specified period of time. When a trigger enters the sub-steady state, neither the output level of the unit can be predicted nor the output stability can be stabilized on a correct level. During this period of stability, the trigger outputs intermediate levels, or may be in an oscillating state, and this useless output level can be propagated along the trigger levels on the signal channel.
Solution:
1. Reduce the system clock
2. Use ff to respond faster
3. Introduce synchronization mechanism to prevent sub-steady state propagation
4. Improve clock quality and use time signals with fast edge changes
The key is that the device requires a large amount of technology and clock period.

7. Differences between Synchronous Reset and Asynchronous Reset in icdesign. 
Synchronous Reset completes the reset operation when the reset signal is acquired along the clock. Asynchronous Reset, regardless of the clock, is completed as long as the reset signal meets the conditions. Asynchronous Reset has high requirements on the reset signal and does not have any glitch. If the relationship between the reset signal and the clock is uncertain, the sub-Steady State may also occur.

8. Moore and meeley state machine features. 
The output of the Moore state machine is only related to the current State value, and the state changes only when the clock edge arrives. the output of the mealy state machine is not only related to the current State value, but also related to the current input value.

9. How to process signals across time domains in Multi-Time Domain Design. 
Synchronous processing is required for signal communication between different clock domains. This prevents the sub-logic from being affected by the sub-logic of the first-level trigger in the new clock domain, for a single control signal, two levels of synchronization can be used, such as level, edge detection, and pulse. For Multiple signals, FIFO, dual-port RAM, and handshake signals can be used.
Cross-time-domain signals must be synced with the synx to prevent sub-steady state transmission. For example, if a signal in the clock domain 1 needs to be sent to the clock domain 2, after the signal is synchronized through the synchronization device in the clock domain 2 before it is sent to the clock domain 2, to enter the clock domain 2. This synchronizator is a two-level D Trigger whose clock is a clock in the clock domain 2. In this case, we are afraid that the signal in the clock domain 1 may not meet the set-up holding time of the trigger in the clock domain 2, but produce the sub-steady state because there is no inevitable relationship between them and it is asynchronous. This can only prevent the spread of the Asian steady state, but cannot ensure the correctness of the collected data. Therefore, only a few digits of the letter are usually synchronized. For example, the control signal or address. When the address is synchronized, the gray code is generally used for this address, because the Gray code changes only one bit at a time, which is equivalent to only one synchronization machine at a time, which can reduce the error rate, this method is used to compare the read/write address size in the asynchronous FIFO design. If a large amount of data is transmitted between two clock domains, asynchronous FIFO can be used to solve the problem.

10. Set setup and hold time for reg to determine the delay range of the intermediate combination logic. 
Delay <period-setup-hold

11. The clock period is T. The maximum output time from the register to the trigger d1 is T1max and the minimum value is T1min. The maximum latency of a combined logical circuit is T2max and the minimum is T2min. Q: What are the conditions for the trigger D2 establishment time t3 and retention time. 
T3setup> T + T2max, t3hold> T1min + T2min

12. Give a diagram of a general time series circuit, including tsetup, tdelay, tck-> q, and clock delay. write out the factors that determine the maximum clock and give an expression. 
T + tclkdealy> tsetup + TCO + tdelay;
Thold> tclkdelay + TCO + tdelay;

13. Advantages and Disadvantages of static and dynamic time series simulation. 
Static time series analysis uses an exhaustive analysis method to extract all time series paths of the entire circuit and calculate the propagation delay of signals on these paths, check whether the signal establishment and retention time meet the time sequence requirements. Analyze the maximum and minimum path latencies to find errors that violate the time sequence constraints. It does not need to input vectors to exhaust all paths, and runs fast and occupies less memory. It not only can perform a comprehensive timing Function check on the chip design, the results of time series analysis can also be used to optimize the design. Therefore, static time series analysis is increasingly used in the verification of digital integrated circuit design.
Dynamic Time series simulation is a common simulation, because it is impossible to generate a complete test vector, covering every path in the door-level network table. Therefore, some possible timing problems on paths cannot be exposed in Dynamic Time Series Analysis;

14. A level-4 MUX, where the second-level signal is the key signal to improve timing.
Key: place the second-level signal to the final output first-level output, and modify the chip selection signal to ensure that its priority is not modified.

15. Why is the width-to-length ratio of the P-tube larger than that of the N-tube in a standard inverted phase device? 
It is related to the carrier. The P-tube is hole-conducting, and the N-tube is electron-conducting. The mobility of electrons is greater than that of holes. Under the same electric field, the current of N-tube is greater than that of the P-tube, symmetric so that the rising time of the two is equal, the noise margin of the high and low levels is the same, and the charging and discharging time is equal.

16. What is the difference between latch and register? Why do we use register now to describe how latch is generated at the behavior level.
Latch is a Level Trigger, register is an edge trigger, and register is triggered at the same clock edge. It conforms to the design philosophy of the synchronous circuit, while latch is an asynchronous circuit design, timing Analysis is often difficult, and improper latch application will waste a lot of chip resources.

17. Differences between blocking and nonblocking assignment. 
Non-blocking Value assignment: The value assignment statement in the block is assigned at the same time, which is generally used in the time series circuit description.