Write makefile with me (3)

Makefile Overview
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I. What is in makefile?

Makefile contains five main items: explicit rules, concealed rules, variable definitions, file instructions, and annotations.

1. explicit rules. Explicit rules demonstrate how to generate one or more target files. This is clearly pointed out by makefile writers that the files to be generated, the dependent files of the files, and the generated commands.

2. Concealed rules. Since make has the function of automatic derivation, obscure rules allow us to write makefile roughly, which is supported by make.

3. variable definition. In makefile, we need to define a series of variables, which are generally strings. This is a bit of a macro in your c language. When makefile is executed, all the variables are extended to the corresponding reference location.

4. File instructions. It consists of three parts: one is to reference another makefile in a makefile, just like the include in C; the other is to specify the valid part of The makefile according to some situations, just like pre-compiled # If in C; there is also the definition of a multi-line command. I will discuss this part in the subsequent sections.

5. comment. Makefile only contains line comments. Like a Unix shell script, the comments use the "#" character, which is like "//" in C/C ++. If you want to use the "#" character in your makefile, you can escape it by using the reversed box, for example, "/#".

Finally, it is worth mentioning that the command in makefile must start with the [Tab] key.

Ii. MAKEFILE file name

By default, the make command searches for files named "gnumakefile", "makefile", and "makefile" in sequence in the current directory and finds the file to be interpreted. Among the three file names, it is best to use the "makefile" file name, because the first character of the file name is in upper case, so there is a clear sense of purpose. It is best not to use "gnumakefile", which is identified by GNU make. Some other make files are only sensitive to all lowercase "makefile" file names, but basically, most make files support "makefile" and "makefile" default file names.

Of course, you can use other file names to write makefile, such as: "Make. linux "," make. solaris "," Make. if you want to specify a specific makefile, you can use the "-F" and "-- file" parameters of make, such as make-F make. linux or make -- file make. aix.

3. Reference other makefiles

You can use the include keyword in makefile to include other makefiles, which is similar to the # include keyword in C language. The contained files are stored in the original mode of the current file. The include syntax is:

Include <FILENAME>

Filename can be the file mode of the current operating system shell (including paths and wildcards)

There may be some null characters before include, but it must not start with the [Tab] key. Include and <FILENAME> can be separated by one or more spaces. For example, you have several makefiles:. MK, B. MK, C. MK, there is also a file named Foo. make, and a variable $ (bar), which contains e. MK and F. MK, then, the following statement:

Include Foo. Make *. mk $ (bar)

It is equivalent:

Include Foo. Make a. mk B. mk C. mk E. mk F. mk

When the make command starts, it searches for other makefiles specified by include and places the files in the current location. It is like the # include command of C/C ++. If no absolute or relative path is specified for the file, make will first search for it in the current directory. If no absolute or relative path is found in the current directory, make will also find it in the following directories:

1. If the "-I" or "-- include-Dir" parameter exists during make execution, make will search for it in the directory specified by this parameter.
2. If the directory <prefix>/include (generally:/usr/local/bin or/usr/include) exists, make will also find it.

If a file is not found, make generates a warning message without a fatal error. It will continue to load other files. Once the makefile is read, make will retry the unfound or unreadable files. If it still does not work, make will produce a fatal message. If you want make to ignore unreadable files and continue execution, you can add a minus sign "-" before include. For example:

-Include <FILENAME>
It indicates that no errors occur during the include process. The commands related to make compatibility with other versions are sinclude, which serves the same purpose as this one.

Iv. environment variables makefiles

If your current environment defines the environment variable makefiles, make will perform an Include-like action on the value of this variable. The values in this variable are other makefiles separated by spaces. However, unlike include, the "target" of the makefile introduced in this environment change does not work. If an error is found in the file defined in the environment variable, make will ignore it.

However, we recommend that you do not use this environment variable here, because as long as this variable is defined, all makefiles will be affected when you use make, this is not what you want to see. This is just to tell you that there may be some strange things in your makefile, so you can check whether the variable is defined in the current environment.

V. How make works

The execution steps of GNU make are as follows: (similar to other make statements)

1. Read all makefiles.
2. Read Other makefiles to be included.
3. initialize the variables in the file.
4. Deduce hidden rules and analyze all rules.
5. create dependency links for all target files.
6. Determine the targets to be regenerated Based on the dependency.
7. Run the generated command.

Step 1-5 is the first stage, and step 6-7 is the second stage. In the first phase, if the defined variable is used, make will expand it to the position in use. But make will not be fully expanded immediately. Make uses the procrastination strategy. If the variable appears in the dependency rule, it will only be used when the dependency is determined, variable is expanded within it.

Of course, you do not have to be clear about this method, but you will be more familiar with make. With this foundation, the subsequent sections will be easy to understand.

 

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