Write makefile with me (2)

3. How does make work?

By default, we only enter the make command. So,

1. Make will find the file named "makefile" or "makefile" in the current directory.
2. If it is found, it will find the first target file (target) in the file. In the above example, it will find the file "edit, and use this file as the final target file.
3. If the edit file does not exist or is later than the edit file. O if the file modification time of the file is newer than that of the edit file, the file will be generated by executing the command defined later.
4. If. o file also exists, so make will find the target in the current file. o file dependency. If found, it will be generated based on that rule. o file. (This is a bit like a stack process)
5. Of course, your c files and H files exist, so make will generate. o file, and then use. o The ultimate task of file life make, that is, execution file edit.

This is the dependency of the entire make. Make will find the dependency of the file layer after layer until the first target file is finally compiled. In the process of searching, if an error occurs, for example, if the dependent file cannot be found, make will exit directly and report an error. For the defined command error, or the compilation fails. Make does not care. Make only depends on the file dependency, that is, if the file after the colon is still not found after I find the dependency, I am sorry, I will not work.

Through the above analysis, we know that such commands as clean are not directly or indirectly associated with the first target file, and the commands defined after it will not be automatically executed. However, we can show that you want to execute make. That is, the command -- "make clean" to clear all target files for re-compilation.

So in our programming, if this project has been compiled, when we modify one of the source files, such as file. c. Then, based on our dependencies, our target file. O will be re-compiled (that is, the command defined after this dependency), so file. O files are also up-to-date, so file. the file modification time of O is newer than that of edit, so edit will be relinked (For details, refer to the Command defined after the target file of Edit ).

If we change "command. H", KDB. O, command. O, and files. O will be recompiled, and edit will be relinked.

4. Use variables in makefile

In the above example, let's take a look at the edit rules:

Edit: Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o
CC-O edit main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

We can see [. o] the file string is repeated twice. If our project needs to add a new [. o] file, so we need to add it in two places (three places, and one place in clean ). Of course, our makefile is not complex, so we are not tired of adding it in two places. However, if makefile becomes complex, we may forget a place to be added, leading to compilation failure. Therefore, variables can be used in makefile to facilitate maintenance of makefile. The makefile variable is a string, which may be better understood as a macro in C language.

For example, we declare a variable named objects, objects, objs, objs, OBJ, or obj. Whatever it is, you just need to be able to represent the OBJ file. We defined this at the beginning of makefile:

Objects = Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Therefore, we can easily use this variable in the "$ (objects)" method in our makefile, so our improved makefile will look like the following:

Objects = Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Edit: $ (objects)
CC-O edit $ (objects)
Main. O: Main. c defs. h
CC-C main. c
KBD. O: KBD. c defs. H command. h
CC-c kbd. c
Command. O: Command. c defs. H command. h
CC-C command. c
Display. O: Display. c defs. h buffer. h
CC-C display. c
Insert. O: insert. c defs. h buffer. h
CC-C insert. c
Search. O: search. c defs. h buffer. h
CC-C search. c
Files. O: files. c defs. h buffer. H command. h
CC-C files. c
Utils. O: utils. c defs. h
CC-C utils. c
Clean:
Rm edit $ (objects)

So if a new. o file is added, you only need to modify the objects variable.

I will give you more things about variables in the future.

V. Make auto-Derivation

GNU make is very powerful. It can automatically deduce the commands behind the file and file dependency, so we do not need to go to every [. o] The files are all written with similar commands, because our make will automatically identify and deduce the commands by ourselves.

As long as make sees [. o] file, it will automatically [. c] Add the file to the dependency. If make finds a whatever. o, then whatever. c, it will be whatever. o. And CC-C whatever. C will also be deduced, so our makefile no longer needs to be written so complicated. Our new makefile is released again.

Objects = Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Edit: $ (objects)
CC-O edit $ (objects)

Main. O: defs. h
KBD. O: defs. H command. h
Command. O: defs. H command. h
Display. O: defs. h buffer. h
Insert. O: defs. h buffer. h
Search. O: defs. h buffer. h
Files. O: defs. h buffer. H command. h
Utils. O: defs. h

. Phony: clean
Clean:
Rm edit $ (objects)

This method is called "concealed rules" of make ". In the above file content, ". Phony" indicates that clean is a pseudo-target file.

For more detailed "concealed rules" and "pseudo-target files", I will give you one by one in the future.

6. Alternative makefile

Now that our make command can be automatically deduced, I can see the heap [. o] and [. h] dependencies are a little uncomfortable, so many repeated [. h]. can I collect it together? Well, no problem. This is very easy for make. Who calls it to provide the function of automatically deriving commands and files? Let's take a look at the latest makefile style.

Objects = Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Edit: $ (objects)
CC-O edit $ (objects)

$ (Objects): defs. h
KBD. O command. O files. O: Command. h
Display. O insert. O search. O files. O: Buffer. h

. Phony: clean
Clean:
Rm edit $ (objects)

This style makes our makefile very simple, but our file dependency is a bit messy. The fish and the bear's paw cannot have both. It also shows your preferences. I don't like this style. First, the dependency between files is unclear. Second, if there are more files and a few new. O files need to be added, it's hard to understand.

VII. Rules for clearing the target file

Each makefile should write a rule to clear the target file (. O and execution file), which not only facilitates re-compilation, but also facilitates file cleaning. This is a "Cultivation" (Oh, remember my "programming Cultivation ). The general style is:

Clean:
Rm edit $ (objects)

A more robust approach is:

. Phony: clean
Clean:
-RM edit $ (objects)

As mentioned earlier,. Phony indicates that clean is a "pseudo target ",. The addition of a small minus sign in front of the RM command means that some files may have problems, but don't worry, continue to do the following. Of course, the clean rule should not be placed at the beginning of the file. Otherwise, it will become the default goal of make. I believe no one would like this. The unwritten rule is: "clean is always placed at the end of the file ".

The above is an overview of makefile, which is also the basis of makefile. There are still many details about makefile. Are you ready? If you are ready, come.

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