x86 virtual address-to-Physical address mapping learning

Here we talk about the mechanism of paging management and the most important memory management mechanism at present.

The original design idea:

The structure diagram is as follows:

The page size is 4KB, the first 20 bits of the virtual address are used to specify a physical page, and the last 12 bits are used to access the in-page offsets.

Structure of page Table entries:

Meaning of the individual bits:

p--bit 0 is the presence (Present) flag that indicates whether the table entry is valid for address translation. P=1 is valid; p=0 means invalid. During page conversion, if the table entry for the page directory or page table involved is invalid, an exception is caused. If P=0, the rest of the bits are free for the program, as shown in 4-18b, except that the table entry is invalid. For example, the operating system can use these bits to hold the ordinal of a page that has been stored on disk.

r/w--bit 1 is a read/write (read/write) flag. If it equals 1, the page can be read, written, or executed. If 0, indicates that the page is read-only or executable. The r/w bit does not work when the processor is running at the Super User privilege level (level 0, 1, or 2). The R/W bit in the page catalog item works for all pages that it maps.

u/s--bit 2 is the user/Super User (User/supervisor) flag. If it is 1, programs running at any privileged level can access the page. If 0, the page can only be accessed by programs running on the Super User privilege level (0, 1, or 2). The U/S bit in the page catalog item works for all pages that it maps.

a--bit 5 is the visited (accessed) flag. This Flag for page table entries is set to 1 when the processor accesses pages for page table entry mappings. When the processor accesses any page of the page Catalog table entry mapping, this flag of the page catalog table entry is set to 1. The processor is only responsible for setting the flag, and the operating system can count the usage of the page by periodically resetting the flag.

d--bit 6 is the page has been modified (DIRTY) flag. When the processor performs a write operation on a page, the D flag for the corresponding page table entry is set. The processor does not modify the D flag in the page catalog entry.

avl--the field is reserved for use by the program. The processor will not modify these, nor will the subsequent upgrade processors.

Because the page table takes up too much memory space (1M elements *4b size =4MB, you can see this: the virtual address space of each process =4g, the page size =4k, so there are 1M pages, need 1M page table entries, and because each page table entry =4b, so the page table size =4m), in order to reduce memory consumption, Therefore, a hierarchical paging structure is designed: Page Catalog table + page table.

Hierarchical design ideas:

Because 4GB of virtual memory has a total of 1m=220=1048576 4K size pages.

We divide these pages into 210 = 1024 parts, that is, from page Table 1 to Page table 1024, by the page catalog table management;

Each (each page table) has 210 = 1024 pages, managed by each page table, the page in the page table is random, which page in which page table is not regular;

The structure diagram is as follows:

Each task has such a hierarchical paging structure that each task has its own page Catalog table and page table.

From the hardware point of view:

In the processor, there is a control register CR3, which holds the physical address of the current task page directory, is also called the page Directory base register (pages directory base REGISTER,PDBR), each task has its own page directory physical address, when the task switch, The processor switches to the new task to begin execution, updating the contents of the CR3 register to point to the page directory location of the new task;

Accordingly, the page directory also points to a page table, each page table and according to the task of the page table item points to the corresponding page. Note that the page directory and page table is also a normal page, in all the physical pages, they are different from the normal page is only the function is not the same, when the task is revoked, they are occupied with the task of the normal page will be recycled, and assigned to other tasks (as shown).

The following transfer from the "paging mechanism", written very clearly.

The specific process of address transformation

For Intel processors, the simplest and most basic mechanism for paging is these; The CR3 register gives the physical address of the page directory; The page directory gives the physical address of all the page tables, and each page table gives the physical address of the pages it contains. Well, the clear is clear, the only thing that does not understand is how to use this hierarchical paging structure to translate the linear address into a physical address? Here, for example, after a task is loaded, a segment is created in the 4GB virtual address space, with a starting address of 0x00800000, a segment boundary of 0x5000, and a granularity of bytes. When the current task executes, the segment register DS points to that segment. And assuming that the following instruction is executed

1. mov edx, [0x1050]

At this point, the segment assembly outputs the linear address 0x00801050. This is the physical address to be accessed when the paging mechanism is not turned on. But now the paging mechanism is turned on, so this is the next virtual address, to be converted by a page part to get the physical address.

As shown, the page part of the processor is specifically responsible for translating the linear address to the physical address. It first sends the segment part of the 32-bit linear address is divided into 3 segments, respectively, the height of 10 bits, the middle 10 bits, low 12 bits. The high 10 bits are the index of the page directory, the middle 10 bits are the index of the page table, and the lower 12 bits are used as the offset in the page.

The physical address of the current task page directory is in the processor's CR3 register, assuming its contents are 0x00005000. The linear address of the segment management part output is 0x00801050, which is given in the binary form. The high 10-bit is the hexadecimal 0x002, which is the index within the page catalog table, and the processor multiplies it by 4 (because each directory entry is 4 bytes), which accesses the page directory as an offset. The final processor obtains the physical address of the page table from physical address 00005008 0x08001000.

The middle 10 bits of the linear address are 0x001, which the processor uses as the page table index to get the physical address of the page. Multiply the value by 4 to access the page table as an offset. Finally, the processor gets the physical address of the page from the physical address 08001004, which is the page we've been trying to find.

The physical address of the page is 0x0000c000, and the low 12 bits of the linear address are the offset of the page in which the data resides. So the processor adds them and gets the physical address 0x0000c050, which is the physical address of the linear address 0x00801050, and the data to be accessed is here.

Note that this transformation is not unprovoked, but is arranged in advance. When the task loads, the operating system creates the virtual segment and determines which page catalog entries and page table entries it will use, based on the high 20 bits of the segment address. Then, look for the free page, write the data that should have been written to the segment into one or more pages, and fill in the page's physical address with the corresponding page table entry. The only way to do this is to change the address in reverse order and find the correct data when the program is running.

Page catalog items, page table entries, CR3, and Page table entries open page-by-page catalog items

Page catalogs and page tables are stored as page Catalog items and page table entries, in the following format:

As you can see, in both the page directory and the page table, only the high 20 bits of the page table or the physical address of the page are saved. The reason is simple, the page table or the physical address of the page must be 4KB aligned, so that it can be placed in a page, so its low 12 bits are all 0. In this case, you can only care about its high 20-bit, low 12-bit arrangement for other purposes.

• P is the presence bit, which is 1 o'clock, which indicates that the page table or page is in memory. Otherwise, the page table or page is not in memory, it must be created, or it can be used before it is transferred from disk to memory.
• RW is a read/write bit. 0 indicates that such a page can only be read, and is 1 readable and writable
• US is the user/management bit. For 1 o'clock, all privileged-level programs are allowed access; As 0 o'clock, only programs with privileged levels of 0, 1, and 2 are allowed access.
• The PWT (Page-level write-through) is a page-level write bit, which is related to caching. "Pass-write" is a way of working with the processor cache, which is used to indirectly decide whether to use this method to improve the efficiency of page access.
• PCD (page-level cache Disable) is a page-level cache disable bit that indirectly determines whether the page that the table item points to uses a cache policy.
• A is the access bit. This bit is set by the processor firmware to indicate whether the page to which this table item points is accessed.
• D (Dirty) is a dirty bit. This bit is set by the processor firmware to indicate whether the page to which this table item points is writing data
• The PAT (page Attribute table) page property sheet supports bits. This bit involves a more complex paging system, which is related to page caching and can be disregarded, and in a normal 4KB paging mechanism, the processor recommends placing it 0.
• G is the global bit. Used to indicate whether the page the table item points to is global in nature. If the page is global, it will persist in the cache (which means that the address translation will be fast). Because the page cache capacity is limited, only those table entries that are frequently used can be stored. Furthermore, the contents of the entire page cache are refreshed when the contents of the CR3 register are changed for reasons such as task switching.
• The AVL bit processor is ignored and the software can be used.

CR3 (PDBR) and open paging mechanism

The control register CR3, which is the page directory table base register PDBR, is shown in the register.

Since the page catalog table must be in a natural page (4KB aligned), the low 12 bits of its physical address are all 0. The low 12 bits are not used except for PCD and PWT. This two-bit cache feature for controlling the page directory is explained above.

The highest-bit PG bit of the control register CR0, which is used to turn paging or turn off the page function. When this bit is clear 0 o'clock, the page function is closed, and the linear address from the segment part is the physical address. When it is placed, the page function is turned on. Paging can only be turned on in protected mode, when the PE bit clear 0 o'clock (real mode), setting the PG bit will cause the processor to produce an abnormal interrupt.

Non-existent page table:

Using a Level Two table structure does not solve the problem of having to use 4MB of memory to store page tables. In fact, we have made the problem a little bit more complicated. Because we need to add another page to store the table of contents. However, the Level two table structure allows page tables to be scattered across memory pages without needing to be stored in contiguous 4MB blocks of memory. In addition, there is no need to allocate a Level two page table for non-existent or linear address space unused portions. Although the Catalog table page must always exist in physical memory, the Level two page table can be redistributed when needed. This allows the size of the page table structure to correspond to the actual linear address space size used.

Each table item in the page catalog table also has an existing (present) property, similar to the table entry in the page table. The existence attribute in the page Catalog table entry indicates whether the corresponding Level two page table exists. If the Catalog table entry indicates that the corresponding Level two page table exists, then by accessing the level two table, the 2nd step of the table lookup process will continue as described above. If there is a bit indicating that the corresponding level two table does not exist, then the processor generates an exception to notify the operating system. The presence attribute in the Page Catalog table entry allows the operating system to allocate level two page table pages based on the range of linear addresses that are actually used.

The presence bit in the Catalog table entry can also be used to hold a Level two page table in virtual memory. This means that at any time only some of the two-level page tables need to be stored in physical memory, while the rest can be saved on disk. Page catalog entries that correspond to page tables in physical memory are labeled as present to indicate that they are available for paging conversions. Page catalog entries for page tables that are on disk will be labeled as nonexistent. The exception that is thrown because the two-level page table does not exist notifies the operating system to load the missing page table from the disk into physical memory. Storing the page table in virtual memory reduces the amount of physical storage that is required to save the paging conversion table.

Summary: Given the virtual address, how to find its corresponding physical address? Two steps!

The first step from the virtual address to the linear address, the second step from the linear address from the physical address.
The first step generates a linear address from the segment base plus the segment offset described by the segment descriptor.
IA32 in the linear address high 10-bit is the page directory index, through this find the page table, the linear address of the middle 10 is the page table item index, through the page table found earlier, add this index, find the page table entry. The page table entry indicates the page frame number, and the page frame number with a linear address low of 12 bits (in-page offset) generates a physical address.

x86 virtual address-to-Physical address mapping learning