Zedboard How to control DDR read/write from PL end (i)

looking at the DDR manual for a while, feeling a little bit about it, want to actually board debugging, but the lab is not much usable development Board, took a piece of ZYNQ board looked, DDR does have, but has integrated the controller, and the controller is placed on the PS end, PL can only be accessed through the Axi interface.

But the other two development boards also like this, simply use Axi to control it, just can also review the Axi again.

A brief introduction to the ZYNQ, its full name is Zedboard Zynq Evaluation and Development Kit, FPGA chip model is xc7z020clg484-1.

The on-chip contains a rich feature of the dual-core ARM CORTEX-A9 processing subsystem (processing System,ps) and Xilinx 28nm programmable logic (Programmable LOGIC,PL). In addition to the core, PS includes on-chip memory, external memory interface and a large number of peripheral connection interfaces. "Citation: Zynq-7000 Overview"

can see its memory specifications: 512MB DDR3;256MB quad-spi flash;4gb SD Card;

The board block diagram is as follows: We can also clearly see that the DDR is located on the PS side

The arm at the PS end has hardware support for the Axi interface directly, while PL requires the corresponding AXI protocol to be implemented using logic. Xilinx offers off-the-shelf IP such as axi-dma,axi-gpio,axi-datamover to implement the appropriate interface, which can be added directly from the XPS IP list.

Sometimes users need to develop their own defined IP to communicate with PS, and the Vivado Wizard can be used to generate the corresponding IP. User-defined IP cores in Vivado can have axi-lite,axi-full,axi-stream.

Axi-lite has a lightweight, simple structure, suitable for small batch data, simple control occasions. Bulk transfer is not supported, read and write only one word at a time (32bit).

AXI4 interface and Axi-lite almost, just add a function is the bulk transfer, you can continue to a single address for one-time read and write.

The above two are in memory-mapped control mode, that is, arm to the user-defined IP into an address to access, read and write as if reading and writing their own on-chip RAM, programming is also very convenient, less difficult to develop. The cost is that the resource takes up too much, requiring additional read address lines, write address lines, read data lines, write data lines, and write response lines to these signal lines.

Another Axi interface is Axi-stream, a continuous stream interface that does not require an address line (much like a FIFO, read or write all the time). For this type of ip,arm cannot be controlled by the above Memory mapping method (FIFO does not have an address concept), there must be a conversion device, such as the AXI-DMA module, to implement memory-mapped to the streaming interface transformation. Axi-stream is suitable for many occasions: video stream processing, communication protocol conversion, digital signal processing, wireless communication and so on. It is essentially a data path built on a numerical stream that builds continuous data streams from sources such as arm memory, DMA, wireless receive front end, and so on, to a host (such as an HDMI display, audio output, etc.). This interface is suitable for real-time signal processing.

With these official IP and wizard-generated custom IPs above, the user does not need to know too much about the axi timing (unless there is a problem) because Xilinx has encapsulated the details related to Axi timing, and the user only has to focus on their own logic implementations.

Zedboard How to control DDR read/write from PL end (i)