Zedboard Zynq Learning Sobel Edge detection IP Core production according to document XAPP890

Official Document Http://www.xilinx.com/support/documentation/application_notes/xapp890-zynq-sobel-vivado-hls.pdf

Preparatory work

Download project file Http://pan.baidu.com/s/1eQqwjBk This is what I share with Baidu Cloud

If not, you can use the official link https://secure.xilinx.com/webreg/clickthrough.do?cid=193509

Sobel operator Edge Detection principle there's not much to say here.

is a convolution process to extract the edges of a picture

Example

C code is as follows

for (i = 0; i < height, i++) {
for (j=0; j < width; j + +) {
X_dir = 0;
Y_dir = 0;
if ((i > 0 && (i < (height-1)) && (J > 0) && (J < (width-1))) {
for (RowOffset =-1; rowoffset <= 1; rowoffset++) {
for (Coloffset =-1; coloffset <=1; coloffset++) {
X_dir = X_dir + input_image[i+rowoffset][j+coloffset]* Gx[1+rowoffset][1+coloffset];
Y_dir = Y_dir + input_image[i+rowoffset][j+coloffset]* Gy[1+rowoffset][1+coloffset];
}
}
Edge_weight = ABS (X_DIR) + ABS (Y_DIR);
OUTPUT_IMAGE[I][J] = edge_weight;
}

Unzip the downloaded package in your workspace first

So next open Vivado HLS Note not Vivado

Click Open Project

Open the project you just unzipped xapp890\sobel_rd_prj click OK

Have the following interface

This is Eclipse's change.

A CPP file in source

Test file Bench

You can see that there's a main function inside Sobel_test.cpp

Click Generate RTL-level algorithm file

If there is flexnet Licensing error:-5,357

Go to apply for a 30-day trial license Tutorial http://blog.sina.com.cn/s/blog_6759fd540101huec.html

You can see that there are Verilog and VHDL folders under the Syn, which is the generated algorithm

Then click on the HDL file package to pass to EDK

Well, I don't know what's in the back. Don't want to learn, to play