Zt:synpify synthesis, hold signal, timing processing

http://www.actel.com/kb/article.aspx?id=TT1002

Logic Replication vs. Preserve Attributes in Synplicity

In general, synplicity ' s synthesis tool, synplify, would try to replicate logic rather than add buffers to stay within the Stated synthesis constraints. However, this feature are "turned off" if the logic in question contains syn_keep or syn_preserve Attribu TES (these is synplify attributes that allow you to preserve a net or preserve a register-examples is shown below) .

In other words, if you use syn_keep or syn_preserve attributes, your may slow down your design since buff ERs added in series with your logic would reduce your circuit ' s performance.

Examples of syn_keep and syn_preserve:

Attribute Syn_preserve of mysignalname:signal is true;

synplicity directive to preserve a signal and the register that generated it

Attribute Syn_keep of mysignalname:signal is true;

synplicity directive to preserve a signal

Http://www.cnblogs.com/wobeiwangle/p/5755612.html

Preserving logic when using synplify synthesis

This tool automatically optimizes my design when using synplify synthesis.

Of course, this function is good and bad, recently there is a project need to use Chipscope to observe the internal signal, open Inserter is ignorant, the signal list of my design some of the names have been changed, some simply to optimize the lost.

On the Internet, of course, some people ask this question, such as http://www.xilinx.com/support/answers/5249.html provides a/* synthesis Syn_keep = 1 * * syntax to retain their own design.

Then to/* Synthesis Syn_keep = 1 * * For the keyword search, and found other new content, then recorded.

Three grammars were mentioned in the Synopsys FPGA Synthesis Attribute Reference Manual : Syn_keep, Syn_preserve, Syn_noprune and comparison of three grammars.

Syn_keep	Applies only to net and combinational logic, which preserves wire in the synthesis process and does not optimize any of the wire. This syntax can also be used with the register, which can be retained and not become macro when used with register
Syn_preserve	Ensure register is not optimized
Syn_noprune	Ensure that an output blackbox (this blackbox output is not driven by any logic) is not optimized

However, the watch is still very vague, and then look at the synplify Pro for Microsemi Edition the User Guide document preserving Objects from Being Optimized Awa The Y section will have a more in-depth explanation.

To Preserve	Attach	Result
Nets	Use the Syn_keep syntax. Suitable for wire or Reg in Verilog, or signal in VHDL	Preserve net in simulation, synthesis or p&r
Net for probing	Use the Syn_probe syntax. For wire or Reg in Verilog, or signal in VHDL	Keep the internal net to use to observe
Shared Registers	Use the Syn_keep syntax. Input wire or signal for shared register	Keep Duplicate Drive cell
Sequential Component	Use the Syn_preserve syntax. Applies to Reg or module in Verilog, or signal or architecture in VHDL	Reserved fixed value-driven register
Fsm	Use the Syn_preserve syntax. Applies to Reg or module in Verilog, or signal in VHDL	Preserve the output port or internal signal with the value of the State register
Instantiated Components	Use the Syn_noprune syntax. Applicable to module or component in Verilog, or architecture or instance of VHDL	Even if the instance has unused ports, it can be preserved.

This can be summed up:

Syn_keep is most commonly used for Wire,reg and shared register two cases;

Syn_probe for observation purposes can be used in wire or Reg (Chipscope to observe the signal using this syntax should be sufficient);

Syn_preseve is used in register or State Register of fixed value drive (Constant-driven);

The Syn_noprune is used for the instantiated module (instance), even if the module has unused ports, it can keep the module.

Zt:synpify synthesis, hold signal, timing processing