A large data interconnection architecture based on crossover switch

A large data interconnection architecture based on crossover switch

Chao Wang (Wang), member, CCF, ACM, IEEE, Xi Li (Li Xi), Senior member, CCF, member, ACM, IEEE, Xue-hai Zhou (Zhou Cohai), Senior, CCF, Member, ACM, IEEE

The on-chip interconnect architecture poses a serious challenge to the design of multi-core processors in the large data age. In view of the current development trend, in the construction of heterogeneous multi-core system based on FPGA, The interconnection architecture based on cross switch is still a relatively efficient and feasible solution. In this paper, we propose a new chip interconnection strategy based on cross Switch Crais, It is mainly aimed at the interconnection between the microprocessor on chip and the IP core of reconfigurable intellectual property. Crais allows data paths to be automatically configured and dynamically refactored for the run-time characteristics of the application. The prototype system is designed and implemented based on FPGA. Experimental data show that Compared with the other architectures commonly used on FPGA, the Starnet,crais can be upgraded to 7 times times the performance acceleration and only occupy starnet 21%~35% hardware resources.

A large data interconnection architecture based on crossover switch