Demand for zero defects in semiconductor components is growing louder

With the increasing number of electronic components in automobiles, it is necessary to strictly control the quality of semiconductor components in modern automobiles to reduce each Baiwan defect rate (DPM), to minimize the use of electronic components in the field of return and guarantee, and to reduce the failure of electronic components caused by liability problems.

The industry has become increasingly vocal about the need for zero defects in semiconductor components, and semiconductor manufacturers have begun to increase their investment response to meet the needs of car users.

American Automotive electronical Commission aec-q001 specification A general method is recommended, which uses the component average test (part Average Testing,pat) method to remove abnormal parts from the total parts, thus improving the quality and reliability of the components at the supplier stage. For a particular wafer, batch number or part group to be measured, the PAT method can indicate that the total average value falls outside the 6σ test result, any test result that exceeds the 6σ limit of the specific component is considered unqualified and removed from the total part, those parts that have not reached the PAT limit cannot start to ship to the customer, This improves the quality and reliability of the components.

The user requirements for these specifications make the competition between suppliers more intense. There is considerable pressure to improve reliability and reduce defect rates, especially for many of the most important security features currently controlled by semiconductors, such as braking, traction control, power and active stability control systems. The supplier is not only to improve the quality of the parts that have been shipped, but also to minimize the effect of these specifications on their yield. As manufacturing costs continue to fall, the cost of testing is maintained at a relatively constant level, so testing costs in the proportion of manufacturing costs increasing, components of the profit space continues to shrink.

Since most of the yield is not up to the requirements, suppliers must thoroughly evaluate their testing procedures to find alternative test methods and test them from alternative methods until they find the best method. Without sophisticated analysis and simulation tools, suppliers will be able to apply them without fully understanding the impact of these specifications on the supply chain.

To make matters worse, if you blindly apply and omit important tests, the result is no doubt, and reliability can be reduced, even if the components are tested and shipped at the same rate of DPM with the size of PAT. Some vendors seem to believe that pat testing is sufficient in wafer detection, but research has shown that there are many problems with this approach. Pat is the first quality checkpoint in wafer detection, but in the remaining downstream manufacturing process, the number of variables caused by numerous variable factors increases, resulting in more pat exception values when encapsulating the test. If the supplier wishes to introduce high-quality parts, they must perform Pat tests in both the wafer detection and final test phases, and their customers should also promote the application of the method.

Real-time Pat and the method used to process Pat processing is to analyze the latest data in several batch processes and establish a static pat limit for each test that is of interest. The average value of these restrictions is +/-6σ, and is usually incorporated into the test program as a specification upper limit (USL) and a lower specification (LSL). The static Pat limit value must be reviewed and updated at least once every six months.

The preferred method is to calculate the dynamic Pat limit value for each batch or wafer. The dynamic Pat limit value is usually more restrictive than the static Pat limit and clears any exception values that are not in the normal distribution. The most important difference is that the dynamic Pat limit value is based on the wafer or batch operation, thus limiting the value to a continuous change in the material properties used by the wafer or batch. The dynamic Pat limit value operation is average/+ (n*σ) or median//+ (n-strong σ) and cannot be less than the LSL or greater than USL specified in the test procedure.