Facing Exascale Intel announces mic Architecture details

Source: Internet
Author: User
Keywords Aliyun Amazon data center Intel Cloud security supercomputer data center cloud security
Tags aliyun applications based business cloud cloud security company computing

At the SC11 conference in Seattle, Washington, the company unveiled details of the next-generation platform for High-performance Computing (HPC)-based Intel Xeon processors and Intel integrated public core (Intel MIC) architecture, as well as a new, exascale-level implementation of the industry in 2018 Exascale) Performance Research and development investment plan.

In a brief statement at the SC11 conference, Rajeeb Hazra, general manager of Intel Data Center and interconnected Systems Division, introduced the Intel Xeon Processor E5 series, which is the first server processor in the world that supports integrated PCI 3.0 specifications in the chip. PCI 3.0 is expected to provide an interconnect bandwidth of up to pci-e2.0 specifications, which drives the implementation of servers with lower power consumption and higher densities. The new network controller will make full use of the advantages of the PCI 3.0 specification, with the increase of the internal nodes of the high performance computing system to achieve more efficient performance expansion and data transmission.

According to the initial performance benchmarking, the initial floating-point performance per second of the Intel Xeon Processor E5 series is compared to the previous generation of the Intel Xeon Processor 5600 series (flops,floating point Operations/Second, Measured by Linpack is 2.1 times times the former, and its performance when running the actual High-performance computing workload is 70% higher than the former.

"Users ' acceptance of the Intel Xeon E5 processor is beyond our expectations, and it is at the speed of the TOP500 rankings, the fastest of all processor products in Intel's history," Rajeeb Hazra said: "Collect, Analyzing and sharing massive amounts of information is critical to today's research activities, requiring a higher level of processor performance and well-designed technology for this purpose. ”

Intel Xeon Processor E5 's debut in the TOP500 rankings coincided with the 40 anniversary of the advent of the world's first microprocessor (Intel 4004 Processor) and the 10 anniversary of the launch of the Intel Xeon brand. Intel estimates that the performance of the Xeon processor has increased more than 130 times since its release in 2001.

Within two months of shipping to a High-performance computing center, the Intel Xeon Processor E5 series has been used in 10 sets of systems in the TOP500 rankings, which are equipped with and run more than 20,000 of the processors, with cumulative output exceeding 3.4 petajoules per second floating-point operations (PFLOPS) Peak Performance.

As previously announced by Intel, the upcoming Intel Xeon Processor E5 series will also be used for other sets of high-performance computers that will be deployed in the future, including a "stampede" system with a performance of up to Pflops, belonging to the Texas high-level computing center; 1.6 Pflops for performance, "Yellowstone" system belonging to the National Center for Atmospheric Research, 1.6 pflops, a "Curie" system to be used by the French National Large Computing Centre (GENCI); 1.3 Pflops for the International Centre for Fusion Energy Research (IFERC) High-performance computing system, as well as the "Pleiades" systems extension of NASA, which has a performance of more than 1 pflops.

Intel has been shipping the Intel Xeon Processor E5 series to a small fraction of cloud computing and High-performance computing users since September, and plans to sell the new product in the first half of 2012. Intel has now won more than 400 system designs for the processor, close to twice times the number of Xeon 5500 and Xeon 5600 processors, and the industry's demand for its first products is 5500 times greater than the Xeon 5600 and Xeon 20 times processors.

During the SC11 conference, Intel also provided detailed information on its more robust server board and chassis product lines, including products specifically optimized for high-performance computing, which will support the release of the Intel Xeon Processor E5 series.

The first Intel integrated public core processor offering Tflops performance

At the SC11 conference, Intel also reaffirmed its commitment to creating the most efficient and easy to program platform for highly parallelization applications. At the Assembly booth, Intel demonstrated the advantages of the Intel integrated architecture for weather modeling, radiographic scanning, protein folding, and advanced material simulation applications.

The first live display of the "Knights Corner" coprocessor products based on the Intel integrated architecture shows the Intel architecture's ability to provide double-precision floating-point performance (measured by DGEMM) over 1 tflops. This is the first display of this high performance level with a single processor chip impact.

Rajeeb Hazra said: "The first time Intel has demonstrated a high-performance computing system with a performance of Tflops, or in 1997, it was equipped with 9,680 Intel Pentium Pro processors, which are attributed to the" ASCI RED "systems in the US National Laboratory in the state of San Diego. Today, the same performance can only be achieved on a single chip based on the Intel Integrated Core architecture, a milestone that will be engraved on the development of High-performance computing. ”

The "Knights Corner" is the first commercially available Intel integrated nuclear architecture product that will be manufactured using Intel's latest three-tier 22 nano-transistor manufacturing process and will integrate more than 50 cores. After future release, this Intel integrated core product will not only provide high performance from its special architecture design for processing tasks with high parallel workloads, but also be compatible with existing x86 programming models and programming tools.

Rajeeb Hazra points out that the "Knights Corner" coprocessor is unique in that it is not like a traditional accelerator, but more like a full-featured, high-performance compute node that can be accessed and programmed, and it looks like an application that runs its own, A computer that is based on a Linux operating system (independent of the main operating system).

One of the advantages of Intel's integrated infrastructure is the ability to run existing applications without having to move their code into a new programming environment. This would allow scientists to leverage CPU and coprocessor performance on existing x86 applications without having to rewrite the code in other proprietary languages, significantly saving time, cost, and resources.

Intel labs to increase investment in exascale-level computing Labs

At the 2011 International Supercomputing Conference in Hamburg (Analysys supercomputing Conference 2011), Intel announced the implementation of Exascale level (Exascale) performance in 2018 ( This performance is equivalent to the performance of the existing top-level High-performance computing system over a hundredfold, and the power consumption is only one-fold more than the existing top performance computing systems. The basis for achieving this is to work closely with the high-performance computing community. Today, Rajeeb Hazra unveiled several new plans to help achieve this goal.

Intel and the Barcelona Supercomputing Centre (BSC) signed a long-term agreement designed to work with the centre to establish a exascale-level laboratory in Barcelona. The lab will be the fourth Exascale-level research and development laboratory in Europe, following the laboratory of Paris, Germany, Yulisi (Juelich) and Leuven (Lueven), which will focus on scalability issues in programming and run-time systems for Exascale-level high-performance computing system.

In addition, the United Kingdom Committee on Science and Technology (STFC) has signed a memorandum with Intel to jointly develop and test the technology needed for future high-performance computers. According to the agreement, STFC, a computing scientist at the Dartmouth Laboratory in England (Daresbury Laboratory), will work with Intel to test and evaluate Intel's existing and future hardware products using advanced software applications. To ensure that scientists are ready to use Intel's future High-performance computing system.

(Responsible editor: The good of the Legacy)

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