Improve embedded system performance multi-core processor architecture

The processor's design is shifting from increasing the frequency to reducing power consumption, to meet higher performance requirements and to make the power consumption less than many applications can withstand, a significant change in the microprocessor is shifting from frequency to multi-core architecture. This paper analyzes the improvement of the performance of embedded http://www.aliyun.com/zixun/aggregation/9344.html "> System design."





Dual-core microprocessor is the focus of current computing design, in order to meet higher performance requirements and to make the power consumption less than many applications can withstand, the microprocessor is moving from the increasing frequency of development trends to multi-core architecture.





Other important developments are also focused on indicators that provide a higher number of instructions on the Unit power consumption, such as on-chip memory controllers, more advanced Dynamic power Management (DFM), and single instruction multiple data (SIMD) engines.





in the past few years, improved technology and transistor technology are the main ways to improve processor performance, while higher frequencies are the driving force for higher performance. However, the focus recently shifted from frequency to power consumption.





what motivates the focus to change? All along, the main consideration of the design Engineer power problem is the gate circuit charge and discharge caused by the AC component. The transfer of semiconductor technology to 90nm and smaller process sizes introduces important DC power components (also known as leakage power or static power). In fact, the typical leakage current of 90nm design at the same voltage is about 2 to 3 times times that of 130nm design, and the power loss caused by leakage current may account for more than half of the total power consumption of some 90nm devices.





lower-power products are manufactured using low-power processes such as insulating silicon (SOI) technology. Soi can reduce parasitic capacitance, increase the switching frequency by 25% or reduce the power consumption by 20%. Work is also in progress on using dielectric materials with lower power and higher dielectric constant k to be used as gate insulators (Gate insulator), which will make it easier to manufacture and thicker layers than the current silica layer.





higher frequency devices require higher power voltages, so their power consumption is exponentially increased. Higher-frequency processors also increase interrupt latency, which is critical for 8208.html ">" Real-time applications and requires deeper pipelines for the kernel. When the processor executes a directive that has not been preset, the pipeline will be congested causing execution to stop, which can have a serious impact on performance.





other factors have forced chip design engineers to improve performance in new ways. Higher frequencies require additional clock overhead, and the processor needs to establish a certain amount of security margin near the clock edge to ensure proper operation. Because the security margin is approximately unchanged, the amount of time available in a clock cycle will actually be less as the frequency increases. Therefore, increasing the frequency does not increase the performance accordingly.





in this way, System design engineers switch to multi-core processor architecture rather than higher frequency devices to achieve system performance improvements and minimize power consumption. Dual-core microprocessors were originally designed for compute-intensive applications such as servers, and are now used in a wide range of embedded applications.





memory controllers and bridging chips are also integrated with multiple cores on a single wafer. Memory subsystem has always been a bottleneck of high-performance processing systems, the latest development of memory technology, including the introduction of the 2nd generation of double Data rate (DDR2) interface, has made a significant performance improvement. Compared with the single data rate (SDR) technology 133MHz transmission rate, the DDR2 transmission rate is as high as 667MHz. However, because the processor clock rate increases faster, people are beginning to pay more attention to the memory response time.





until recently, many of the system's logic, including memory controllers, were located outside the processor in the form of a North bridge and a bridge chip. The memory controller and bridging chip are integrated into the same wafer as the microprocessor kernel, which can reduce the bottleneck of bandwidth and response time. For example, the on-chip memory controller reduces the latency of processor to storage by 2/3 to 3/4.





some times more importantly, such integration can save board space. Higher integration is especially important for providing stronger processing capability within small sizes such as advanced mezzanine cards (Advanced Mezzanine Cards, AMC). Better memory control can save power. When there is no data to process and no need to refresh, the more intelligent memory controller can make the clock can signal ineffective, so as to avoid unnecessary memory clock, generally can reduce up to 20% of the memory power.





Another system design technique that can be used to reduce the power consumption of memory chips and their end resistors is to use the processor for remote guidance and control when they are connected in a cluster form (clustered arrangement). High-speed interconnection/network solutions, such as RapidIO technology, enable full control of the processor nodes through the connection of the processor node to the architecture. This eliminates the flash memory for the bootstrapper, as well as the various programmable logic devices used to drive resets and interrupts, thereby saving power and circuit board size.





traditional devices such as Ethernet controllers now seem to have the basic function of starting an FTP-based bootstrapper without additional flash memory. In the application of Digital Subscriber line access Multiplexer (DSLAM), the elimination of flash memory on each line card can save about 3W of power for the 32-line DSLAM.




The data input and output of
processor is another focus to improve system performance. New specifications, such as Advanced Communication Computing Architecture (ADVANCEDTCA), also drive the development of high-bandwidth pipelines, which support the ability of several high-performance interconnects on the backplane to be a key advantage of ADVANCEDTCA. So far, each such interconnect requires an external chip.





is now designed for ADVANCEDTCA processor with a high bandwidth pipeline, without external devices can be implemented from the backplane to the processor Gigabit Ethernet, serial RapidIO and pci-express direct connection, which in power, circuit board area, Provides the best solution for development time and system cost.





the integration of such interfaces on the chip also allows optimization of processing between the kernel and the interface. For example, in Gigabit Ethernet modules, interface hardware can perform some early analysis and classification at wire speed, send different types of frames to different buffer pools, and transmit the header frame to the Level 2 cache for faster processing by the microprocessor kernel. This method greatly reduces the burden of the kernel by establishing a processing pipeline between the interface and the kernel.





Embedded Design Engineers can use a variety of opportunities to conserve processor power. For example, dynamic frequency switching (DFS) allows the software to significantly change the kernel frequency of the processor at runtime during a clock cycle, without inserting an empty cycle or resetting the device, and the processor remains intact. This will generally save 45% of the power.