Intel announces eight core processor 24MB Super large three cache technology

At the end of May this year, Intel released some initial data on the upcoming eight-core Nehalem-ex Xeon Server processor, and today specifically passed http://www.aliyun.com/zixun/aggregation/7330.html " > Tech blog explores 24MB Super three cache technology.

The six-core Dunnington Xeon 7400 of the architecture has been expanded to 12/16MB level three cache, and the Xeon 5500/3500 series, which is based on the Nehalem architecture, location dual and single market, is 8MB, then how does 24MB do it? Especially how to manage power consumption?

(Note the new Itanium LOGO)

Intel says that the 24MB three cache of Nehalem-ex Xeon is run in 24-channel, 8-port mode, made from 45nm HKMG process combined with 9-layer copper interconnect, with a storage unit area of 0.3816 Square microns, and the main technologies in power management and power control:

-Use dormant transistor (sleep transistor) to maximize the control of leakage power

-New shutdown option to eliminate leakage of disabled partial cache

-Better clock gating to reduce dynamic power consumption

-Cache independent power supply to run on the lowest operating voltage, while satisfying the target frequency and minimizing the power consumption

-The minimum voltage of the SRAM unit in the shutdown period is only 0.36V, which can reduce the leakage power of about 83%

-a series of other redundant initiatives to ensure the manufacturability of the processor

Intel says it is precisely because of the high density, low power, design reusability, and the adoption of this series of optimization technology to achieve super large capacity of the three cache, both to ensure high performance, but also achieve energy efficiency.