Italian-French semiconductor (ST) and Soitec together with CMP to provide 28 NM fd-soi CMOS process

The Italian-French semiconductor (ST), Soitec and CMP (circuits Multi Projets) work together to announce that universities, research laboratories and design companies will be able to use the silicon Intermediary services of CMP to adopt the CMOS 28 NM fd-soi (fully Depleted Silicon-on-insulator, fully empty-type silicon insulated amorphous crystal Element) manufacturing process design wafer-type, this process uses the Soitec developed innovative silicon substrate. With the completion of the first commercial wafer, the Italian-French semiconductor will contract this process to the third party wafer maker in the near future.

CMP's Product catalog list of intentional semiconductor 28 NM fd-soi CMOS manufacturing process represents the successful cooperation between the two sides, and the cooperation between the Italian-French semiconductor and CMP enables tertiary institutions and design companies to adopt the intended semiconductor generation CMOS design chip, including 45 nanometers (2008), 65 nanometers (2006), 90 nanometers (2004) and 130 nanometers (2003). CMP customers can also use the 65 nm and 130 nm insulating layer silicon wafer (SILICON-ON-INSULATOR,SOI) and the 130 nm SiGe manufacturing process in the Italian-French semiconductor. 170 tertiary institutions and design companies have acquired the 90 nm CMOS manufacturing design rules and tools, more than 200 colleges and universities and design companies have access to the Italian-French semiconductor 65 nm bulk and Soi CMOS manufacturing design rules and tools.

CMP has been providing 28 NM CMOS Bulk technology since 2011, and about 60 universities and microelectronics enterprises have acquired design rules and tools and successfully produced 16 integrated circuits (ICS).

CMP director Bernard Courtois said: "People are interested in the use of these design IC, about 300 project design has been used 90 nm manufacturing process (2009), more than 300 project design has been adopted 65 NM bulk manufacturing process. In addition, more than 60 design projects have been made with 65 nm soi, and it is worth mentioning that in Europe, the United States, Canada and Asia, many prestigious colleges and universities have benefited from cooperation with the Italian and CMP semiconductors. 」

Through CMP multi-project wafer services, academic organizations and design companies can obtain a small number of advanced ICS (from dozens of to thousands of pieces). The 28 nm fd-soi CMOS manufacturing cost is fixed at 18,000€/mm2 and the minimum order quantity is 1mm2.

Philippe Magarshack, executive vice president for design implementation and services at the Italian-French semiconductor, said: "With the first batch of Fd-soi designs nearing completion, it is now the best time to launch this technology into the research field." Our Fd-soi is designed to support the fast and easy porting of existing designs to the Fd-soi platform, resulting in low power and high performance dual advantages. In addition, the advanced technology of the universities and colleges with the purpose of semiconductor technology will also help to attract outstanding young engineers, which is one of our long-term commitments as technical leaders. 」

"Our partnership with Longoria and CMP is the best example of Soitec's commitment to expanding support for Fd-soi ecosystem and advanced technology users and delivering differentiated material solutions to open markets," said Steve Soitec, senior vice president of global strategic business development. This partnership provides reliable next-generation integrated circuit development testing for tertiary institutions and other customers, and we will see innovative products based on Soitec fd-soi materials. 」